Rtl Design Engineer

Sykatiya Technologies Pvt Ltd; Hyderabad, Bengaluru; On-site; INR 2,400,000 - 4,000,000; Full time

Job summary

Sykatiya Technologies Pvt Ltd is seeking an RTL Design Engineer with 5-8 years of experience located in Bangalore or Hyderabad. The role focuses on RTL coding, CDC, linting, and regression checks, with responsibilities spanning synthesis, timing, power estimation, and formal verification in collaboration with Design and DV teams.

The candidate will interact with Physical Design and provide timing/congestion feedback, while developing automation scripts for FE tools to streamline RTL-to-Gate

Qualifications

• Experience: 5-8 years in RTL design and verification.
• Strong expertise in RTL coding, CDC, lint and regression checks.

Responsibilities

• Run Logic/Physical Synthesis and generate optimized gate-level netlists for timing, area, power.
• Debug timing, area, and congestion issues with RTL and physical designers.
• Perform power estimation at RTL and gate level and identify reduction opportunities.
• Run formal verification checks between RTL and gate-level netlists and debug failures.
• Perform RTL lint and work with designers to create waivers.
• Perform RTL DFT analysis and improve DFT coverage for stuck-at faults.
• Develop timing constraints for RTL-synthesis and PrimeTime-STA for blocks and top-level including SOC.
• Develop automation scripts and methodology for FE-tools including Lint, CDC, RDC, Synthesis, STA, Power.

Skills

RTL Coding

CDC

Lint

Regression checks

Timing

Power

Formal Verification

DFT

Synthesis

Automation scripts

Tools

PrimeTime-STA

Synthesis tools

Job description

Role & responsibilities

Job Title: RTL Design Engineer

Experience: 5-8yrs

Location: Bangalore/Hyderabad

About the Role

We are seeking a highly skilled RTL Design Engineer with strong expertise in RTL Coding, CDC, Lint and Regression checks.

In this role, you will work closely the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback.

Responsibilities

• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
• Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.
• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.
• Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures.
• Perform RTL Lint and work with the Designers to create waivers.
• Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults.
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the toplevel including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks.
• Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power)

Preferred candidate profile