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Scaledge is seeking an experienced RTL Design Engineer to design, develop, and implement RTL for complex digital designs across multiple locations in India. The role emphasizes Verilog/SystemVerilog, microarchitecture development, and integration of PCIe, Ethernet, and AMBA IPs.
You will collaborate with architecture, verification, and physical design teams to ensure RTL quality and optimize for PPA. A strong foundation in digital design and ASIC flow is essential.
Job Title: RTL Design Engineer
Experience: 4 - 10 Years
Location: Bangalore, Hyderabad, Ahmedabad, Bhubaneswar, Pune, Noida.
Domain: VLSI / ASIC Design
Job Overview
We are looking for an experienced RTL Design Engineer with strong expertise in RTL coding, microarchitecture, and digital design. The candidate should have hands-on experience in RTL development using Verilog/SystemVerilog and a good understanding of high-speed communication protocols such as PCIe, Ethernet, and AMBA.
Key Responsibilities
Required Skills
Preferred Skills
Education