Rtl Design Engineer

Intellics Global Services; Hyderabad, Bengaluru; On-site; INR 900,000 - 1,800,000; Full time

Job summary

Intellics Global Services is seeking an experienced SoC design engineer in India to contribute to subsystem/IP design and SoC integration, with emphasis on AMBA protocols and RTL quality checks.

You will work with teams across design, verification, and SW to debug issues and review design documents for multiple subsystems, supporting QA and integration efforts.

Qualifications

• Expert in SoC subsystem/IP design.
• Experience in IP design, Subsystem/Cluster and SoC integration.
• RTL quality checks: lint and CDC.
• Knowledge of synthesis and low power is a plus.
• Understanding AMBA protocols AXI/AHB/ATB/APB.
• Understanding timing concepts.
• Experience with PCIe, DDR, Ethernet, I2C/UART/SPI.
• Scripting: Make flow, Perl, shell, Python.
• Ability to support multiple subsystems and reviews.

Responsibilities

• Collaborate on SoC design and integration across subsystems.
• Assist physical design, verification, DFT and SW teams with design queries.
• Create/review design documents for multiple subsystems.
• Provide debugging support for architecture and IP blocks.

Skills

SoC design

IP design

SoC integration

RTL quality checks

AMBA protocols

timing concepts

subsystem interfaces

scripting languages

Tools

Spyglass Lint/CDC

Synopsys DC

Verdi/Xcellium

Job description

Role & responsibilities

Notice : Immediate 60 days

Work Location : Bangalore / Hyderabad

Expertise in SoC subsystem/IP design
Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
In depth knowledge on RTL quality checks (Lint, CDC)
Knowledge of synthesis and low power is a plus
Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
Good understanding of timing concepts
Knowledge of one or more of the interface protocols

• a. PCIe
• b. DDR
• c. Ethernet
• d. I2C, UART, SPI

Expertise in setting up and using tools like

• a. Spyglass Lint/CDC
• b. Synopsys DC
• c. Verdi/Xcellium

Understanding of scripting languages like Make flow, Perl ,shell, python etc
Understanding of processor architecture and/or ARM debug architecture is a plus
Able to help and debug issues for multiple subsystems
Able to create/review design documents for multiple subsystems
Able to support physical design, verification, DFT and SW teams on design queries and reviews

Preferred candidate profile

Perks and benefits