RTL Design Engineer

JOBWORLD INDIA PRIVATE LIMITED; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Benefits offered by this job

Opportunity to work on global semiconductor programs

Exposure to advanced ASIC and SoC development

Long-term career growth in chip design

Job summary

A semiconductor company is seeking a highly skilled RTL Design Engineer in Hyderabad. The role involves converting architecture specifications into scalable RTL and conducting quality checks with SpyGlass. Candidates should have strong RTL coding expertise in Verilog/SystemVerilog and experience with ASIC/SoC design flow. This position offers the chance to work on global semiconductor programs and collaborate with experienced engineering teams for long-term career growth in chip design.

Qualifications

• Strong expertise in RTL coding with Verilog/SystemVerilog.
• Hands-on experience with SpyGlass for checking quality.
• Good understanding of pipelining techniques and datapath architecture.

Responsibilities

• Convert architecture specifications into detailed micro-architecture design.
• Perform RTL quality checks using SpyGlass (Lint, CDC, RDC).
• Design FSMs, datapath logic, and pipelined architectures.
• Collaborate with Design Verification (DV) teams to resolve functional issues.
• Work with synthesis and physical design teams for timing closure.

Skills

RTL coding expertise in Verilog/SystemVerilog

Hands-on experience with SpyGlass (Lint / CDC / RDC)

Pipelining techniques

Datapath architecture

Clock and Reset domain crossings

Tools

SpyGlass

Job description

We are looking for a highly skilled RTL Design Engineer with strong experience in micro-architecture development and RTL implementation. The candidate will be responsible for converting architecture specifications into scalable and synthesizable RTL while ensuring high-quality design through SpyGlass lint and CDC sign-off.

This role offers the opportunity to work on a high-impact Global Foundry program, collaborating with cross-functional teams across design, verification, and synthesis.

Key Responsibilities

• Convert architecture specifications into detailed micro-architecture design
• Perform RTL quality checks using SpyGlass (Lint, CDC, RDC)
• Design FSMs, datapath logic, and pipelined architectures
• Ensure robust clock domain crossing (CDC) and reset domain crossing (RDC) handling
• Collaborate with Design Verification (DV) teams to resolve functional issues
• Work with synthesis and physical design teams for timing closure and implementation readiness
• Follow low-power friendly RTL design practices
• Ensure high-quality RTL sign-off for silicon readiness

Required Skills & Qualifications

• Strong RTL coding expertise in Verilog/SystemVerilog
• Hands‑on experience with SpyGlass (Lint / CDC / RDC)
• Good understanding of:
• Pipelining techniques
• Datapath architecture
• Clock and Reset domain crossings
• Experience working with ASIC/SoC design flow

Good to Have

• Exposure to AMBA protocols (AXI / AHB / APB)
• Experience working on complex SoC designs
• Familiarity with low power design methodologies

Why Join Us

• Opportunity to work on global semiconductor programs
• Exposure to advanced ASIC and SoC development
• Collaboration with highly experienced engineering teams
• Long‑term career growth in chip design and semiconductor engineering

📍 Location Note: This role is based in Hyderabad, and candidates should be open to working from the Hyderabad office.