Senior RTL Design Engineer

Thompsons HR Consulting Pvt Ltd; Bengaluru Urban; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

Thompsons HR Consulting Pvt Ltd in Bengaluru, Karnataka seeks an experienced digital design engineer with 3+ years in semiconductor engineering and a strong background in RTL, Verilog/SystemVerilog, and SoC architecture. The role emphasizes timing, clocking, and DFT/DFD methods to deliver robust designs.

The ideal candidate holds a BS/MS/PhD in EE or related field and has hands-on experience with advanced SoC design, memory BIST, and regression workflows.

Qualifications

• 3+ years of industry experience in digital design / semiconductor engineering.
• BS, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or related discipline.
• Strong experience with digital RTL design, microarchitecture, computer architecture, and advanced SoC design.
• Experience with DFT/DFD logic such as fuse controllers, memory BIST, scan dump, or related infrastructure
• Strong understanding of clocking and reset methodologies.
• Understanding of timing constraints.

Skills

RTL Design

Verilog/SystemVerilog

SoC Architecture

Microarchitecture

Computer Architecture

DFT/DFD

Memory BIST

Clocking

Reset

Timing Constraints

STA

SDC

Timing Closure

CDC

Physical Design

Education

BS in Electrical Engineering

MS/PhD in Electrical Engineering or related discipline

Tools

Python

Ruby

Git

Regression system

Job description

Location: Bengaluru, Karnataka

Experience: 6+ Years

Function: VLSI / Semiconductor / AI Chip Design

Employment Type: Full-Time

Required Qualifications & Experience

• 3+ years of industry experience in digital design / semiconductor engineering.
• BS, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or related discipline.
• Strong experience with digital RTL design, microarchitecture, computer architecture, and advanced SoC design.
• Experience with DFT/DFD logic such as fuse controllers, memory BIST, scan dump, or related infrastructure
• Strong understanding of clocking and reset methodologies.
• Understanding of timing constraints.

Good-to-Have Skills

• Experience working in a startup environment.
• Experience with RTL design for Clock Domain Crossings (CDC).
• Experience with Python or Ruby.
• Experience working with a regression system.
• Experience with a revision control system.
• Comfortable working from the command line

Key Technical Skills

• RTL Design
• Verilog/SystemVerilog
• SoC Architecture
• Microarchitecture
• Computer Architecture
• DFT
• DFD
• Memory BIST
• Scan
• Fuse Controllers
• Clocking
• Reset
• Timing Constraints
• STA
• SDC
• Timing Closure
• CDC
• Physical Design
• Floorplanning
• Placement
• CTS
• Routing
• Power/Timing Optimization
• RTL Regression
• Python/Ruby