RTL Design Engineer (BB46FT RM 4562)

Source-Right; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

Source-Right is seeking an RTL Design Engineer in Bengaluru to independently develop synthesizable RTL for assigned blocks under guidance, collaborating with verification and implementation teams.

You will develop Verilog/SystemVerilog RTL, understand specifications, perform RTL simulations, and support synthesis and timing closure activities, with close collaboration with DV, STA, and PD engineers.

Qualifications

• 4–6 years RTL Design experience.
• Strong Verilog/SystemVerilog coding.
• Digital Design fundamentals.
• FSM concepts and state machines.
• Counters, FIFOs and arbitration logic.
• Pipeline design and reset handling.
• Clock gating and CDC/RDC basics.
• Lint analysis and simulation debugging.
• Synthesis awareness with EDA tools (VCS/Xcelium, Verdi).
• Good debugging and analytical skills.

Responsibilities

• Develop synthesizable Verilog/SystemVerilog RTL.
• Understand design specs and implement block-level functionality.
• Perform RTL simulations and debug failures.
• Resolve lint issues, CDC and RDC violations.
• Support synthesis and timing closure activities.
• Participate in design reviews.
• Prepare RTL documentation.
• Work closely with DV, STA and PD engineers.

Skills

RTL Design

Verilog

SystemVerilog

Digital Design

FSM

Counters

FIFOs

Arbitration

State Machines

Pipeline

Reset handling

Clock gating

CDC basics

RDC basics

Lint analysis

Simulation debugging

Synthesis awareness

VCS/Xcelium

Verdi

Debugging

Tools

Verdi

VCS/Xcelium

Git/Perforce

Python scripting

Job description

Position: RTL Design Engineer (BB46FT RM 4562)

Role Summary

The RTL Design Engineer will independently develop synthesizable RTL for assigned blocks under the guidance of the Technical Lead while collaborating with verification and implementation teams.

Responsibilities

• Develop synthesizable Verilog/System Verilog RTL.
• Understand design specifications and implement block-level functionality.
• Perform RTL simulations and debug failures.
• Resolve
• Lint issues
• CDC violations
• RDC violations
• Support synthesis and timing closure activities.
• Participate in design reviews.
• Prepare RTL documentation.
• Work closely with DV, STA and PD engineers.

Required Skills

• 4–6 years RTL Design experience
• Strong Verilog/System Verilog coding
• Digital Design fundamentals
• FSM
• Counters
• FIFOs
• Arbitration logic
• State Machines
• Pipeline design
• Reset handling
• Clock gating
• CDC basics
• RDC basics
• Lint analysis
• Simulation debugging
• Synthesis awareness
• Familiarity with VCS/Xcelium and Verdi
• Good debugging and analytical skills

Preferred Skills

• AXI/AHB/APB
• UPF basics
• Git/Perforce
• Python/TCL scripting
• FPGA exposure (optional)