RTL Architect

Intellics Global Services; Ernakulam, Hyderabad, Bengaluru; Hybrid; INR 6,000,000 - 9,000,000; Full time

Job summary

Intellics Global Services is seeking a seasoned RTL Architect to define micro-architecture and lead RTL design for complex silicon, owning PPA and design quality through tape-out.

You will partner with DV/DFT/PD, drive timing and power optimizations, mentor RTL teams, and support emulation, FPGA prototyping, and silicon bring-up across multiple SoC projects.

Qualifications

• Extensive RTL design and integration experience with multiple tape-outs.
• Strong Verilog/SystemVerilog and micro-architecture skills.
• Experience with AMBA, NoC, PCIe, DDR/LPDDR, Ethernet, USB.
• Low-power design, clocking, CDC/RDC, timing-driven RTL.
• Front-end tools: lint, CDC, synthesis, STA; scripting in Python/Perl/Tcl.

Responsibilities

• Define micro-architecture and interface specs from system requirements.
• Own PPA trade-offs and RTL quality, plus constraints (SDC, UPF).
• Lead subsystem and SoC integration; drive design/code reviews.
• Collaborate with DV/DFT/PD to address verification and timing.
• Mentor RTL teams; act as escalation point for design issues.
• Support emulation, FPGA prototyping, silicon bring-up, root-cause analysis.

Skills

RTL design

SystemVerilog

Micro-architecture

Mentoring

Tools

Verilog

SystemVerilog

lint

CDC/RDC

Synthesis

STA

Python

Perl

Tcl

UPF

Job description

Role & responsibilities

JOB DESCRIPTION

RTL Architect

Experience

15+ years

Location

Hyderabad, bangalore,chennai,kochi,pune

Domain

ASIC / SoC Turnkey Silicon

Employment

Full-time

The Role

Define micro-architecture and lead RTL design and SoC/subsystem integration for complex silicon, owning PPA and design quality through tape-out.

What You Will Do

• Define micro-architecture, block partitioning and interface specifications from system requirements.
• Own PPA trade-offs and RTL quality: lint, CDC/RDC, synthesis and constraints (SDC, UPF).
• Lead subsystem and SoC integration, and drive design and code reviews.
• Partner with DV, DFT and PD to close verification, testability, timing and power.
• Mentor and technically guide RTL teams; act as the escalation point for design issues.
• Support emulation, FPGA prototyping, silicon bring-up and root-cause analysis.

What You Bring

• 15+ years in RTL design and integration, with multiple tape-outs in a lead or architect role.
• Expert Verilog / SystemVerilog and strong micro-architecture skills.
• Deep experience with AMBA (AXI/AHB/APB), NoC and high-speed interfaces such as PCIe, DDR/LPDDR, Ethernet, USB.
• Solid grasp of low-power design (UPF), clocking, CDC/RDC and timing-driven RTL.
• Proficiency with front-end tools: lint, CDC, synthesis, STA; scripting in Python, Perl or Tcl.
• Clear technical communication with customers and cross-functional teams.

Good to Have

• ARM or RISC-V subsystem integration
• Die-to-die / UCIe and chiplet architectures
• Post-silicon debug experience