RTL Design Engineer

Gtc Informatics Private Limited; India; Remote; INR 900,000 - 1,500,000; Full time

Job summary

GTC Informatics Private Limited is seeking experienced RTL Design Engineers for semiconductor projects across India. Roles can be full-time or contract, depending on client requirements, and quick joiners are encouraged to apply.

You will design micro-architecture and RTL blocks, write clean Verilog/SystemVerilog, run lint and CDC checks, support synthesis and timing closure with physical design teams, and collaborate with verification teams to debug design issues.

Qualifications

• 4-10 years of RTL design for ASIC/SoC
• Strong hands-on skills in Verilog and SystemVerilog
• Experience with lint and CDC tools such as Spyglass
• Good understanding of synthesis, STA and timing constraints (SDC)
• Knowledge of protocols such as AXI, AHB, APB or PCIe
• Good debugging and communication skills

Responsibilities

• Work on micro-architecture and RTL coding of IP blocks and subsystems
• Write clean, synthesizable RTL using Verilog/SystemVerilog
• Run lint, CDC and RDC checks and fix issues
• Support synthesis and timing closure with physical design teams
• Work with verification teams to debug and close design issues
• Prepare design documents and specifications

Skills

RTL design

Verilog

SystemVerilog

Lint/CDC tools (Spyglass)

Synthesis & timing (SDC)

Bus protocols (AXI/AHB/APB/PCIe)

Debugging & communication

Job description

About the Role:

GTC Informatics Private Limited is hiring experienced RTL Design Engineers for semiconductor design projects across India. These positions are open on both a full-time and contract basis, depending on client and project requirements. Experienced candidates who can join quickly are encouraged to apply.

Location : PAN INDIA

Roles & Responsibilities:

• Work on micro-architecture and RTL coding of IP blocks and subsystems
• Write clean, synthesizable RTL using Verilog/SystemVerilog
• Run lint, CDC and RDC checks and fix issues
• Support synthesis and timing closure with physical design teams
• Work with verification teams to debug and close design issues
• Prepare design documents and specifications

Required Skills & Experience:

• 4-10 years of experience in RTL design for ASIC/SoC
• Strong hands-on skills in Verilog and SystemVerilog
• Experience with lint and CDC tools such as Spyglass
• Good understanding of synthesis, STA and timing constraints (SDC)
• Knowledge of protocols such as AXI, AHB, APB or PCIe
• Good debugging and communication skills

Good to Have:

• PCIe or high-speed interface design experience
• Low-power design knowledge (UPF/CPF)
• ing skills in Python, Perl or Tcl