RTL design

Tech Andhra; Hyderabad; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Tech Andhra is seeking RTL Synthesis Engineers (SOC Design Implementation) to Hyderabad onsite. The role requires 4–8 years of experience in RTL synthesis and STA/LEC/SDC constraints. You will drive timing closure and signoff activities with DFT/PD teams, using tools like Design Compiler, Genus, and Conformal.

Work onsite in Hyderabad and contribute to high-performance, power-efficient SOC designs. Strong emphasis on timing and constraints across functional and test modes.

Qualifications

• RTL synthesis expertise to optimize performance, power and area using Design Compiler, Fusion Compiler, Genus.
• Setup timing constraints for functional and test modes.
• Familiarity with Conformal for LEC and equivalence checks.

Responsibilities

• RTL synthesis to optimize performance, power and area using Design Compiler, Fusion Compiler, Genus.
• Setup timing constraints for functional and test modes.
• Verify logic equivalency checks RTL→Gates and Gates→Gates using Conformal.
• Setup signoff STA and ECO flows with Design/DFT/PD teams to achieve timing closure.
• Timing analysis with STA tools such as PrimeTime and Tempus.
• Constraints debugging and sanity checks.

Skills

RTL Synthesis

STA and Timing closure

LEC

SDC Constraints

Job description

Role:

RTL Synthesis engineers -SOC Design Implementation Engineer

Location:

Hyderabad - Onsite

Expereince:

4 - 8 yrs exp

Design Implemenation:

• RTL Synthesis to achieve the best Performance/Power/Area of the designs - Design Compiler, Fusion Compiler, Genus.
• Setup Timing Constraints for functional and Test Modes.
• Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates - Conformal.
• Setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams.
• Timing analysis with STA tools - PrimeTime, Tempus
• Constraints debug and sanity checks.

Required Skills:

• RTL Synthesis
• STA and Timing closure
• LEC (Logic and Equivalence Check)
• SDC Constraints