Senior Physical Design Engineer

NXP Semiconductors; Maharashtra; Hybrid; INR 2,800,000 - 5,500,000; Full time

Benefits offered by this job

Health insurance

Job summary

NXP Semiconductors in India seeks an experienced Senior Physical Design Engineer to drive the physical implementation of complex SoCs from netlist to GDSII, ensuring timing, power, area and reliability targets are met.

You will lead floorplanning, CTS, routing, timing closure, and PD signoff while mentoring juniors and collaborating with RTL, Synthesis, DFT, STA, and Signoff teams on global projects.

Qualifications

• Bachelor's or Master's in Electronics, VLSI, Electrical Engineering, or related field.
• Hands-on experience in physical design for complex SoCs/IP blocks.
• Proficiency with standard EDA tools for PD and signoff.

Responsibilities

• Own end-to-end physical design implementation of complex digital blocks/subsystems.
• Drive floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification.
• Perform design optimization for PPA targets.
• Execute timing closure across multiple operating modes and process corners.
• Collaborate with RTL, Synthesis, DFT, STA, Package, and Signoff teams to hit milestones.
• Support ECO implementation and tapeout activities.
• Develop and enhance PD methodologies, automation flows, and scripts.
• Review design quality and mentor junior engineers.
• Work closely with global cross-functional teams.

Skills

Floorplanning

Power planning

Placement optimization

Clock Tree Synthesis

Routing

Timing closure

Physical verification

Education

Bachelor's or Master's in Electronics

Tools

Cadence Innovus

Synopsys ICC2

PrimeTime

Tempus

RedHawk/Voltus

StarRC/Quantus

Calibre

Job description

Job Title: Senior Physical Design Engineer

Location

Pune / Bangalore / Hyderabad (Hybrid)

Experience

8-10 Years

Job Summary

We are seeking a highly motivated and experienced Senior Physical Design Engineer to join our VLSI Physical Design team. The candidate will be responsible for delivering high-quality physical implementation of complex SoC/IP blocks from netlist to GDSII, ensuring timing, power, area, and reliability targets are met. The ideal candidate should have hands‑on expertise in advanced node design implementation and signoff methodologies.

Key Responsibilities

• Own end-to-end physical design implementation of complex digital blocks/subsystems.
• Drive floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification.
• Perform design optimization for PPA (Power, Performance, Area) targets.
• Execute timing closure across multiple operating modes and process corners.
• Analyze and resolve setup, hold, SI, IR-drop, EM, and congestion issues.
• Collaborate with RTL, Synthesis, DFT, STA, Package, and Signoff teams to achieve project milestones.
• Support ECO implementation and tapeout activities.
• Develop and enhance PD methodologies, automation flows, and scripts to improve productivity.
• Review design quality and mentor junior engineers.
• Work closely with global cross-functional teams.

Required Technical Skills

• Strong expertise in:
  • Floorplanning
  • Power Planning
  • Placement Optimization
  • Clock Tree Synthesis (CTS)
  • Routing
  • Timing Closure
  • Physical Verification

STA & Signoff

• In-depth knowledge of:
  • Static Timing Analysis (STA)
  • Multi-Mode Multi-Corner (MMMC) methodologies
  • Crosstalk/SI Analysis
  • ECO Flows
  • Timing Signoff

Physical Signoff

• Experience with:
  • IR Drop Analysis
  • Electromigration (EM) Analysis
  • DRC/LVS Closure
  • Reliability Checks

Hands-on Experience With Industry-standard EDA Tools

• Cadence Innovus
• Synopsys ICC2
• PrimeTime
• Tempus
• RedHawk / Voltus
• StarRC / Quantus
• Calibre

Educational Qualification

• Bachelor's or Master's Degree in Electronics, VLSI, Electrical Engineering, or related field.

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