DFX Verification Engineer

Tessolve; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Tessolve in Bengaluru, India is seeking a verification engineer to develop and execute verification plans for DFx features including scan, MBIST/LBIST, and boundary scan (JTAG). You will create and maintain testbenches using SystemVerilog/UVM for robust DFx validation.

Responsibilities include verifying scan chain integrity, test mode functionality and coverage, ATPG pattern validation, and debugging. You will contribute to BIST controllers and memory test logic, leveraging tools like VCS,

Qualifications

• DFT concepts including Scan, ATPG, MBIST, JTAG.
• Expertise in SystemVerilog and UVM.
• Simulation tools: VCS, Xcelium, Questa.
• Familiarity with ATPG tools: TetraMAX, Modus, FastScan.
• Debug tools: Verdi, DVE.
• Understanding of clocking and reset strategies.

Responsibilities

• Develop and execute verification plans for DFx features including Scan, MBIST/LBIST and Boundary Scan (JTAG).
• Create and maintain testbenches using SystemVerilog/UVM for DFx validation.
• Verify scan chain integrity, test mode functionality and coverage; validate ATPG patterns and debugging.
• Develop BIST controllers and memory test logic.

Skills

DFT concepts

SystemVerilog

UVM

Scan design

Tools

VCS

Xcelium

Questa

Verdi

DVE

TetraMAX

Modus

FastScan

Job description

Key Responsibilities

• Develop and execute verification plans for DFx features including:
• Scan (stuck-at, transition fault)
• MBIST / LBIST
• Boundary Scan (JTAG)
• Memory repair and redundancy
• Create and maintain testbenches using SystemVerilog/UVM for DFx validation
• Verify:
• Scan chain integrity and connectivity
• Test mode functionality and coverage
• ATPG pattern validation and debug
• BIST controllers and memory test logic

Technical Skills

• Strong knowledge of:
• DFT concepts (Scan, ATPG, MBIST, JTAG)
• Expertise in: SystemVerilog and UVM
• Simulation tools (VCS, Xcelium, Questa)
• Familiarity with: ATPG tools (TetraMAX, Modus, FastScan)
• Debug tools (Verdi, DVE)
• Understanding of:
• Clocking and reset strategies