Senior DFT Verification Engineer

NVIDIA Gruppe; Bengaluru; On-site; INR 800,000 - 1,500,000; Full time

Job summary

NVIDIA Gruppe is seeking a DFT Verification Engineer based in Bangalore, Karnataka. The role involves ensuring flawless execution in dynamic projects via dedicated DFT verification and silicon bring-up.

The ideal candidate will own end-to-end DFX verification and work closely with various teams to improve DFT methodologies for next-generation products. A BSEE or MSEE with 3+ years of experience is required.

Qualifications

• 3+ years of experience in DFX verification and silicon bring-up.
• Proficiency in RTL and gate verification.
• Familiarity with BIST architecture and JTAG standards.

Responsibilities

• Take ownership of DFX verification and silicon bring-up.
• Collaborate with teams to improve DFT methodologies.
• Help develop and deploy DFT methodologies for next-generation products.

Skills

Static timing analysis

ECO

ASIC/Logic Design Flow

HDL

Digital logic design

Scripting knowledge (Perl or Python)

Education

BSEE or MSEE

Job description

Join NVIDIA as a DFT Verification Engineer based in Bangalore, Karnataka. Your role will focus on ensuring flawless execution of dynamic projects through dedicated DFT verification and silicon bring‑up.

What you'll be doing:

• Take end‑to‑end ownership of DFX verification, pattern development, and silicon bring‑up for a range of test features—including JTAG, boundary scan, security mechanisms, reliability tests like HTOL/IDDQ, and test clocking—across various test modes, including multiple ATPG configurations in multi‑die environments.
• Work closely with various DFX teams, CAD, and methodology teams to improve flows and processes.
• Help develop and deploy DFT methodologies for next‑generation products.
• Be part of innovation efforts to improve the quality of DFT methods and AI deployment processes.
• Collaborate with multi‑functional teams to incorporate DFT features into the chip.

What we need to see:

• BSEE or MSEE from reputed institutions or equivalent experience with 3+ years of experience.
• Proficiency in static timing analysis, ECO, ASIC/Logic Design Flow, HDL, and digital logic design.
• Experience in RTL and gate verification, simulation, and silicon bring‑up.
• Familiarity with BIST architecture and JTAG/IEEE1149.1/1500/1687/1838.
• Strong DFT knowledge in Scan ATPG, compression techniques, and memory test.
• Strong analytical and problem‑solving skills with good scripting knowledge (either Perl or Python).