DFT verification engineer

Acldigital; Hyderabad; On-site; INR 1,000,000 - 1,400,000; Full time

Job summary

A leading tech company in Hyderabad is seeking a DFT Verification Engineer to develop and execute pre-silicon verification plans. The role involves verifying DFT design blocks and debugging regression test failures, requiring strong programming skills in Verilog and C++. Candidates should have 3 to 5 years of experience in DFT feature verification and familiarity with EDA tools. This position offers a great opportunity to work in a dynamic environment and contribute to advanced chip validation.

Qualifications

• 3 to 5 years of experience in DFT feature verification (JTAG, MBIST, SCAN, fuse, IO-PHY testing).
• Strong debug skills and experience with debug tools.
• Familiarity with EDA simulation tools.

Responsibilities

• Develop and execute pre-silicon verification test plans for DFT features.
• Verify DFT design blocks and subsystems using complex SV or C++ environments.
• Debug regression test failures and optimize test patterns.

Skills

Programming skills in Verilog

Programming skills in C++

Strong debug skills

Experience with debug tools like Verdi

Experience with scripting languages (Tcl, Perl, Ruby, Python)

Working knowledge of Unix/Linux OS

Education

Engineering Degree in Electronics/Electrical/Computer Science

Tools

Synopsys VCS

Cadence NCSIM

Job description

DFT Verification Engineer

What are the responsibilities in this role?

• Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality.
• Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or C++ verification environments. Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation.
• Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
• Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs.

Qualifications and Experience

• 3 to 5 year experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing).
• Strong programming skills in Verilog and/or C++.
• Strong debug skills and experience with debug tools such as Verdi.
• Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi.
• Experience with any scripting languages like Tcl/Perl/Ruby/Python.
• Working knowledge of Unix/Linux OS and file version control.

Educational Background

Minimum Engineering Degree in Electronics/Electrical/Computer Science.