DFT Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru, India is seeking an experienced DFT Engineer with 5+ years of hands-on DFT/ASIC experience. The role focuses on design-for-test implementation, verification, pattern generation, and sign-off for complex ASIC/SoC designs.

You will develop and verify DFT architectures, perform scan insertion, compression, ATPG, and test pattern generation, and work on MBIST/LBIST. Collaboration with RTL, DV, and PD teams is essential.

Qualifications

• 5+ years of hands-on DFT/ASIC experience.
• Develop and verify DFT architecture from spec to sign-off.
• Implement scan insertion, scan compression, ATPG, and test patterns.
• MBIST/LBIST implementation and verification.
• JTAG, IJTAG, boundary scan, and test access mechanisms.
• Develop and validate DFT constraints and ensure DFT rule compliance.
• Perform DFT simulations and debug test-related issues.
• Validate ATPG patterns and analyze fault coverage.
• Collaborate with RTL, DV, PD, STA, and other teams to resolve DFT issues.
• Automate DDFT flows and reporting using TCL, Python, or Shell scripting.
• Support post-silicon test/debug activities when required.

Responsibilities

• Develop and implement DFT architecture for complex ASIC/SoC designs.
• Perform scan insertion, scan compression, ATPG, and test pattern generation.
• Work on MBIST/LBIST implementation and verification.
• Implement and debug JTAG, IJTAG, boundary scan, and test access mechanisms.
• Develop and validate DFT constraints and ensure DFT rule compliance.
• Perform DFT simulations and debug test-related issues.
• Validate ATPG patterns and analyze fault coverage.
• Collaborate with RTL, DV, PD, STA, and other teams to resolve DFT-related issues.
• Support DFT integration at block and full-chip levels.
• Analyze and improve fault coverage metrics.
• Debug scan chain, compression, clock, reset, and test-mode issues.
• Support DFT timing and physical implementation requirements.
• Participate in DFT sign-off activities and provide reports.
• Automate DFT flows and reporting using TCL, Python, or Shell scripting.
• Support post-silicon test/debug activities when required.

Skills

DFT/ASIC

Scan Insertion

ATPG

MBIST

JTAG/IJTAG

Boundary Scan

Scripting

Education

Bachelors/Masters in Electronics/Electrical/Microelectronics

Tools

Synopsys

Cadence

Siemens EDA/Mentor

Job description

We are looking for an experienced DFT Engineer with 5+ years of hands-on experience in Design-for-Test (DFT) implementation and verification for complex ASIC/SoC designs. The ideal candidate should have strong expertise in scan insertion, ATPG, MBIST, JTAG/IJTAG, DFT verification, and test pattern generation/validation.

The candidate will be responsible for executing DFT activities from specification and architecture through implementation, verification, pattern generation, and sign-off.

Key Responsibilities

• Develop and implement DFT architecture for complex ASIC/SoC designs.
• Perform scan insertion, scan compression, ATPG, and test pattern generation.
• Work on MBIST/LBIST implementation and verification.
• Implement and debug JTAG, IJTAG, boundary scan, and test access mechanisms.
• Develop and validate DFT constraints and ensure DFT rule compliance.
• Perform DFT simulations and debug test-related issues.
• Validate ATPG patterns and analyze fault coverage.
• Work closely with RTL, Design Verification, Physical Design, STA, and other teams to resolve DFT-related issues.
• Support DFT integration at block and full-chip levels.
• Analyze and improve stuck-at, transition, and other fault coverage metrics.
• Debug scan chain, compression, clock, reset, and test-mode issues.
• Support DFT timing and physical implementation requirements.
• Participate in DFT sign-off activities and provide required reports and documentation.
• Automate DFT flows and reporting using TCL, Perl, Python, or Shell scripting.
• Support post-silicon test/debug activities when required.

Required Skills

• 5+ years of relevant DFT/ASIC experience.
• Strong hands-on experience with:
• Scan insertion
• ATPG
• Scan compression
• MBIST
• JTAG / IJTAG
• Boundary Scan
• DFT verification
• Good understanding of ASIC/SoC design and DFT methodologies.
• Experience with DFT tools from Synopsys, Cadence, Siemens EDA/Mentor, or equivalent.
• Strong knowledge of ATPG fault models and coverage analysis.
• Experience with simulation and pattern validation.
• Good understanding of test clocks, test modes, scan chains, resets, and clock-domain considerations.
• Strong debugging and problem-solving skills.
• Good scripting knowledge in TCL / Python / Perl / Shell.
• Ability to work effectively with cross-functional semiconductor design teams.

Good to Have

• Experience with advanced DFT architectures and large SoCs.
• Exposure to hierarchical DFT implementation and full-chip integration.
• Experience with IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG).
• Knowledge of low-power DFT methodologies.
• Experience with DFT requirements for advanced technology nodes.
• Exposure to physical-design-aware DFT implementation.
• Experience with DFT sign-off and silicon bring-up/debug.

Education

• Bachelor's or Master's degree in Electronics & Communication Engineering, Electrical Engineering, Microelectronics, or a related field.