DFT Engineer

Shashwath Solution; Dadri; On-site; INR 600,000 - 1,200,000; Full time

Job summary

Shashwath Solution in India is seeking an engineer proficient in Verilog/VHDL RTL coding to work with Mentor DfT and Cadence tools. The role emphasizes hands-on scan insertion, JTAG and ATPG, DRC, and coverage analysis, along with timing-aware simulation debugging.

LBIST and Mixed Signal Radar IC experience is highly desirable. The candidate must be proactive, collaborative, and detail-oriented with strong communication and independent judgment.

Qualifications

• Hands-on experience in Verilog/VHDL RTL coding.
• Strong debugging and problem-solving abilities for simulations.
• Experience with scan insertion, JTAG, ATPG, DRC and coverage analysis.
• LBIST and Mixed Signal Radar IC experience is highly desirable.
• Proactive, collaborative, and detail-oriented with independent judgment.

Responsibilities

• RTL design and verification using Verilog/VHDL.
• Apply scan insertion, JTAG, ATPG, DRC and coverage analysis.
• Debug simulations and perform root-cause analysis for timing/SDF issues.
• Collaborate with cross-functional teams and communicate technical findings clearly.

Skills

RTL design skills

Independent judgment

Collaboration

Communication skills

Tools

Mentor DfT tools

Cadence tools

Job description

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools.

• The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
• Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable
• Must be proactive, collaborative and detail-oriented capable of exercising independent judgment
• The engineer with experience on debug and root cause the problem in simulation failures
• Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.