Stand out for this role — generate a tailored resume and cover letter in about a minute.
Shashwath Solution in Pune district seeks an experienced verification/design engineer with strong RTL coding in Verilog/VHDL and hands-on DFT knowledge, including scan insertion, JTAG, ATPG and timing analysis. Proficiency with Mentor DfT and Cadence tools is desirable.
Ability to debug and root-cause simulation failures is essential. The candidate should be proactive, collaborative, with excellent communication skills and a detail-oriented approach, capable of independent judgment in fast-paced
The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools.