Design Verification Engineer (DV)

Nanodroits Technologies; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Nanodroits Technologies seeks a Design Verification Engineer with 3+ years of ASIC/SoC verification experience to join our semiconductor verification team in Bengaluru. You will own the verification process from testbench development through to functional closure, ensuring complete coverage and bug-free silicon.

Responsibilities include building UVM-based environments, writing SystemVerilog assertions, creating verification plans, executing simulations, debugging RTL results, and coordinating

Qualifications

• 3+ years of hands-on ASIC/SoC design verification experience.
• Strong proficiency in SystemVerilog and UVM.
• Deep understanding of functional coverage and constrained-random testing.
• Excellent debugging capabilities and cross-functional collaboration.

Responsibilities

• Testbench development: create reusable UVM environments for IP/SoC verification.
• Verification planning: design test plans for functional, corner-case, and negative scenarios.
• Simulation & Debug: run simulations, debug failures, and root-cause RTL issues.
• Coverage: develop functional and code coverage models and close gaps.
• Assertions: write SystemVerilog Assertions to verify protocol behavior.
• Regression: set up regression suites and triage nightly failures.
• Formal verification: apply formal methods for block-level checks when possible.
• Cross-functional: align verification with RTL design, DFT, and architecture teams.

Skills

SystemVerilog

UVM

Functional coverage

Constrained-random testing

Debugging

Team collaboration

Education

Bachelors or Masters in Electrical/ Electronics/ Computer Engineering

Tools

Synopsys VCS

Cadence Xcelium

Verdi/SimVision

Job description

We are seeking a skilled and detail-oriented Design Verification Engineer with 3+ years of experience to join our semiconductor verification team. In this role, you will be responsible for developing and executing verification plans for complex, high-performance IP blocks and SoC subsystems. You will own the verification process from testbench development through to functional closure, ensuring complete coverage and robust, bug-free silicon.

Role & responsibilities

• Testbench Development: Develop and maintain UVM-based, reusable verification environments for IP and SoC-level verification.
• Verification Planning: Create comprehensive verification test plans covering functional, corner-case, and negative scenarios.
• Simulation & Debug: Execute simulations, debug failures using waveform viewers, and root-cause issues down to RTL.
• Coverage Closure: Develop functional and code coverage models; analyze and close coverage gaps.
• Assertion-Based Verification: Write System Verilog Assertions (SVA) to verify protocol and design behavior.
• Regression Management: Set up and maintain regression suites; triage and debug nightly regression failures.
• Formal Verification: Apply formal methods/tools for targeted block-level property checking where applicable.
• Cross-functional Collaboration: Work closely with RTL design, DFT, and architecture teams to align verification with design intent.

Required Qualifications

• Experience: Minimum 3+ years of hands-on industry experience in ASIC/SoC design verification.
• Education: Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Verification Languages/Methodology: Strong proficiency in System Verilog and UVM.
• Tools: Experience with industry-standard simulators (Synopsys VCS, Cadence Xcelium) and debug tools (Verdi/SimVision).
• Technical Skills: Deep understanding of functional coverage, assertion-based verification, and constrained-random testing.
• Soft Skills: Excellent debugging capabilities, strong teamwork, and clear communication skills to collaborate with RTL and DFT teams.
• Technology: worked on technology node 3nm, 5nm, 7nm.
• Technical Skills: Deep understanding of functional coverage, code coverage, assertion-based verification, GLS simulation, Regression and constrained-random testing.
• Protocols: AXI, APB, AHB, PCIe, UCIe, CXL etc.