DFT Engineer (DFT Feature Verification) — 3–5 Years

Best NanoTech; Hyderabad; Sur place; INR 1 500 000 - 2 000 000; Plein temps

Résumé du poste

A leading technology firm in Hyderabad is seeking a DFT Engineer with 3–5 years of experience in DFT feature verification for ASIC/SoC. The role involves verifying critical DFT features including JTAG and SCAN, developing verification tests, and collaborating with cross-functional teams. Candidates should be proficient in Verilog/SystemVerilog and scripting languages such as Python and Tcl, and have strong debugging skills using tools like Verdi. This is a full-time position with opportunities for growth.

Qualifications

• 3–5 years of relevant experience in DFT feature verification for ASIC/SoC.
• Strong hands-on verification experience.
• Strong programming ability in Verilog/SystemVerilog and/or C++.

Responsabilités

• Verify DFT features at IP/SoC level including JTAG/TAP, SCAN, MBIST.
• Develop verification environments and tests using Verilog/SystemVerilog.
• Drive debug and root-cause analysis for simulation failures.
• Run and manage regressions on industry simulators.
• Create automation utilities to improve regression and reporting.
• Collaborate with design/DFT/validation teams.
• Ensure clean deliverables and well-structured checklists.
• Work effectively in Linux/Unix environments.

Connaissances

Verification experience with JTAG

Verification experience with SCAN

Verification experience with MBIST

Programming in Verilog/SystemVerilog

Simulation debug capability using Verdi

Scripting in Python

Scripting in Tcl

Scripting in Perl

Scripting in Ruby

Experience with Linux/Unix

Outils

Synopsys VCS

Cadence NCSim

Xcelium

Git

Perforce

SVN

Description du poste

Overview

Location: Hyderabad, India | Work type: Full-time

Role Overview: We are looking for a DFT Engineer (3–5 years) to work on DFT feature verification at SoC/ASIC level. The role focuses on building and executing verification for DFT-related blocks and flows such as JTAG, SCAN, MBIST, fuse, and IO-PHY loopback testing, along with strong debug ownership using industry-standard simulators and waveform/debug tools.

Responsibilities

• Verify DFT features at IP/SoC level including JTAG/TAP, SCAN, MBIST, fuse programming behavior, and IO/PHY loopback modes.
• Develop/modify verification environments and tests using Verilog/SystemVerilog (and/or C++ where applicable).
• Drive debug and root-cause analysis for simulation failures using tools like Verdi (waveform, connectivity, X-prop, assertions as applicable).
• Run and manage regressions on industry simulators such as Synopsys VCS and/or Cadence NCSim/Xcelium.
• Create automation utilities using Python/Tcl/Perl/Ruby to improve regression, log parsing, coverage collection, and reporting.
• Collaborate with design/DFT/validation teams to clarify test intent, corner cases, and feature expectations.
• Ensure clean deliverables: reproducible tests, clear debug notes, and well-structured checklists for feature sign-off.
• Work effectively in Linux/Unix environments and follow team workflows for version control and code reviews.

Required Qualifications

• 3–5 years of relevant experience in DFT feature verification for ASIC/SoC.
• Strong hands-on verification experience with JTAG, SCAN, MBIST, fuse, and IO-PHY loopback testing.
• Strong programming ability in Verilog/SystemVerilog and/or C++.
• Strong simulation debug capability using Verdi (or equivalent, with Verdi preferred).
• Experience with simulators such as Synopsys VCS and/or Cadence NCSim/Xcelium.
• Scripting experience in Python / Tcl / Perl / Ruby for automation.
• Comfortable working in Linux/Unix and using version control (Git/Perforce/SVN).
• Exposure to structured regression infrastructure, log triage automation, and basic coverage-driven closure.
• Familiarity with SoC bring-up considerations for test features and low-power effects on DFT logic.