DFT Engineer

Mirafra Technologies; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Mirafra Technologies in Bengaluru is seeking a hands-on DFT Engineer to drive ASIC/SoC DFT development, including scan insertion, ATPG, and DRC.

You will collaborate with RTL, Synthesis, STA, and Verification teams, verify DFT at RTL and gate level, and automate flows with Tcl/Python/Shell.

Qualifications

• Hands-on experience in ASIC/SoC DFT and scan methodology.
• Experience with ATPG, scan compression, DFT DRC, and fault coverage.
• Knowledge of MBIST/LBIST, JTAG, and Boundary Scan is a plus.
• Proficiency in Verilog/SystemVerilog and Linux.
• Experience with industry tools such as Synopsys TestMAX/TetraMAX, Cadence Modus, or Siemens Tessent.

Responsibilities

• Develop and implement DFT architecture for ASIC/SoC designs.
• Perform scan insertion, scan stitching, scan compression, and DFT DRC.
• Generate and debug ATPG patterns for faults.
• Analyze and improve fault coverage and debug untestable faults.
• Work on MBIST/LBIST, JTAG/Boundary Scan as required.
• Perform DFT verification at RTL and gate level.
• Define and debug test-mode and scan timing constraints.
• Collaborate with RTL, Synthesis, STA, Physical Design, and Verification teams.
• Support DFT sign-off and tape-out activities.
• Automate DFT flows using Tcl/Python/Perl/Shell.

Skills

ASIC DFT

ATPG

Scan compression

DFT DRC

Fault coverage

MBIST/LBIST

JTAG/Boundary Scan

Verilog/SystemVerilog

Linux

Tcl/Python

Tools

Synopsys TestMAX/TetraMAX

Cadence Modus

Siemens Tessent

Job description

Looking for a DFT Engineer with hands-on experience in DFT implementation, scan insertion, ATPG, scan compression, coverage analysis, and DFT verification for ASIC/SoC designs.

Key Responsibilities

• Develop and implement DFT architecture for ASIC/SoC designs.
• Perform scan insertion, scan stitching, scan compression, and DFT DRC.
• Generate and debug ATPG patterns for stuck-at and transition faults.
• Analyze and improve fault coverage and debug untestable/aborted faults.
• Work on MBIST/LBIST, JTAG/Boundary Scan as required.
• Perform DFT verification at RTL and gate level.
• Define and debug test-mode and scan timing constraints.
• Collaborate with RTL, Synthesis, STA, Physical Design, and Verification teams.
• Support DFT sign-off and tape-out activities.
• Automate DFT flows using Tcl/Python/Perl/Shell.

Required Skills

• Strong knowledge of ASIC DFT and scan methodology.
• Experience with ATPG, scan compression, DFT DRC, and fault coverage.
• Knowledge of MBIST, LBIST, JTAG, and Boundary Scan is a plus.
• Proficiency in Verilog/SystemVerilog and Linux.
• Experience with tools such as Synopsys TestMAX/TetraMAX, Cadence Modus, or Siemens Tessent.