DFT Engineer

Neurealm; Pune District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Neurealm in Pune seeks a seasoned DFT/ASIC test engineer to drive scan insertion, ATPG vector generation, and fault analysis across STA and At-Speed domains. You will collaborate with RTL/netlist teams and ATE partners to ensure robust DFT flows and successful bring-up.

The role emphasizes hands-on MBIST, boundary scan, and scripting in Perl/TCL to automate test workflows, with exposure to Mentor, Synopsys, and Cadence toolchains.

Qualifications

• Hands-on experience in inserting scan and generating ATPG vectors for fault models (Stuck-At, At-Speed).
• Experience in MBIST insertion and simulation.
• Experience in Boundary Scan, inserting tap controllers and P1500.
• Experience in RTL-based and netlist-based insertion flows.
• Experience in DFT simulation with/without SDF; synthesis and formal verification tools.
• Experience in characterization (DC characteristics).
• Experience in generating TDL for ATE and working with ATE team during bring-up phase.
• Exposure to DFT tools from Mentor, Synopsys and Cadence.
• Good scripting know-how in Perl and TCL.
• Experience in Static Timing analysis preferred.

Skills

ATPG vector insertion

DFT fault analysis

MBIST insertion/simulation

RTL/netlist insertion flows

Synthesis and formal verification

DC characteristics

TDL scripting for ATE

Perl scripting

TCL scripting

Education

BE/ME or BTech/MTech

Tools

Mentor tools

Synopsys tools

Cadence tools

Scripting languages (Perl/TCL)

Job description

Skills and Experience Required

• Hands on experience in Inserting Scan and generating ATPG vectors for
• Stuck-At and At-Speed Faults. In-depth experience in analysing and improving scan coverage
• Hands on experience in MBIST (insertion and simulation)
• Experience in Boundary Scan, inserting tap controller and P1500
• Experience in RTL based and netlist-based insertion flows
• Experience in DFT simulation with and without SDF Experience in Synthesis and formal verification tools
• Experience in characterization (DC Characteristics)
• Experience in generating TDL for ATE and working closely with ATE team during bring-up phase
• Good exposure to DFT tools from Mentor, Synopsys and Cadence
• Good scripting know-how in Perl and TCL
• Experience in Static Timing analysis preferred

Educational Qualification: BE/ME or BTech /MTech