DFT Engineer | Noida | 5+

Erbity; Ahmedabad District; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Erbity is seeking a hands-on DFT engineer to drive scan insertion, ATPG generation, coverage closure, and pattern validation for complex IC designs in Noida. The role requires deep experience with scan and MBIST, boundary scan, TAP controller, and IEEE 1500/P1500, plus RTL/netlist DFT flows and DFT verification tools.

The ideal candidate brings DC characterization experience, scripting in Perl/TCL, and exposure to STA.

Qualifications

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults.
• Strong experience in scan coverage analysis and improvement.
• Hands-on experience in MBIST insertion and simulation.
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.
• Experience with RTL and netlist-based DFT flows.
• Experience in DFT simulation with and without SDF.
• Working knowledge of Synthesis and Formal Verification tools.
• Experience in DC characterization.
• Experience generating TDL for ATE and supporting silicon/ATE bring-up.
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor.
• Good scripting skills in Perl and TCL.
• Exposure to Static Timing Analysis (STA) is preferred.

Responsibilities

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams.
• Support DFT activities through tapeout and silicon bring-up.

Skills

Scan Insertion

ATPG Stuck-at

ATPG At-Speed

Scan coverage

MBIST insertion

Boundary Scan

TAP Controller

IEEE 1500

RTL DFT

DFT netlists

DFT simulation

Synthesis

Formal Verification

DC characterization

ATE bring-up

DFT tools (Synopsys Cadence Mentor)

Perl scripting

TCL scripting

Static Timing Analysis

Education

BE/BTech/ME/MTech

Tools

Synopsys

Cadence

Siemens EDA/Mentor

Job description

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults


• Strong experience in scan coverage analysis and improvement


• Hands-on experience in MBIST insertion and simulation


• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500


• Experience with RTL and netlist-based DFT flows


• Experience in DFT simulation with and without SDF


• Working knowledge of Synthesis and Formal Verification tools


• Experience in DC characterization


• Experience generating TDL for ATE and supporting silicon/ATE bring-up


• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor


• Good scripting skills in Perl and TCL


• Exposure to Static Timing Analysis (STA) is preferred

Location:

Noida

Qualification:

BE/BTech/ME/MTech

Key Skills & Experience

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults


• Strong experience in scan coverage analysis and improvement


• Hands-on experience in MBIST insertion and simulation


• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500


• Experience with RTL and netlist-based DFT flows


• Experience in DFT simulation with and without SDF


• Working knowledge of Synthesis and Formal Verification tools


• Experience in DC characterization


• Experience generating TDL for ATE and supporting silicon/ATE bring-up


• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor


• Good scripting skills in Perl and TCL


• Exposure to Static Timing Analysis (STA) is preferred

Work

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation


• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows


• Work closely with Design, Verification, PD, STA, and ATE teams


• Support DFT activities through tapeout and silicon bring-up

Ideal Profile:

Strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up.