Dft Design Engineer

Skywaves Rise; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Skywaves Rise seeks a Lead DFT Engineer to own the DFT architecture and sign-off for complex SoCs. You will drive Scan Insertion, MBIST, and ATPG while coordinating with RTL, Physical Design, STA and Test teams to ensure silicon quality and efficient test flow.

You will develop automation scripts to improve productivity and flow efficiency, with a strong emphasis on verification, debug, and test coverage optimization across advanced technology nodes.

Qualifications

• Hands-on experience in Design for Test (DFT) for complex SoCs.
• Expertise in Scan Insertion, scan compression, and scan architecture.
• Deep MBIST implementation, integration, and verification experience.
• Strong ATPG generation, fault simulation, and coverage optimization knowledge.

Responsibilities

• Define and implement DFT architecture for complex SoCs and IPs.
• Drive Scan Insertion, compression, stitching, and verification.
• Develop and integrate MBIST solutions for memories and repair workflows.
• Generate and optimize ATPG patterns for various fault models.
• Perform DFT verification, coverage analysis, pattern validation, and debugging.
• Collaborate with RTL, PD, STA, and Test teams to close DFT gaps.

Skills

Design for Test

Scan Insertion

MBIST

ATPG

Scripting (TCL/Python)

Debugging

Cross-functional collaboration

Tools

Siemens Tessent

Synopsys TestMAX/DFT Compiler

IEEE 1149.1 / boundary scan

Job description

About the Role

We are looking for a Lead DFT Engineer to drive Design-for-Test implementation for complex SoCs across advanced technology nodes. You will own DFT architecture, implementation, and sign-off with a strong focus on Scan Insertion, MBIST, and ATPG, enabling high-quality silicon with optimal test coverage.

What You'll Do

• Define and implement DFT architecture for complex SoCs and IPs.
• Drive Scan Insertion, scan compression, scan stitching, and scan verification.
• Develop and integrate MBIST solutions for embedded memories and memory repair flows.
• Generate and optimize ATPG patterns for stuck-at, transition, and advanced fault models.
• Perform DFT verification, coverage analysis, pattern validation, and debug.
• Collaborate with RTL, Physical Design, STA, and Test Engineering teams to achieve DFT closure.
• Drive DFT sign-off, improve test coverage, and optimize test time and silicon quality.
• Develop automation scripts to improve DFT productivity and flow efficiency.

What We're Looking For

• 1012 years of hands-on experience in Design for Test (DFT).
• Strong expertise in Scan Insertion, scan compression, and scan architecture.
• Deep experience with MBIST implementation, integration, and verification.
• Strong knowledge of ATPG generation, fault simulation, and coverage optimization.
• Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, or equivalent.
• Understanding of JTAG/IEEE 1149.1, boundary scan, and IEEE 1500 standards.
• Experience with DFT validation, gate-level simulation, and scan debug.
• Proficiency in TCL, Python, or Perl scripting for flow automation.
• Excellent debugging, analytical, and cross-functional collaboration skills.