DFT Engineer | Noida | 5+

Erbity; Dadri; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Erbity is seeking a hands-on DFT Engineer in Noida to drive DFT insertion, ATPG generation, coverage closure, and pattern validation across RTL and gate-level flows. You will collaborate with Design, Verification, PD, STA, and ATE teams to ensure robust testability and smooth tapeout progression.

The ideal candidate has extensive experience in MBIST, boundary scan, ATPG, and DFT tools, with scripting skills in Perl/TCL and familiarity with STA. Noida-based role with silicon bring-up involvement.

Qualifications

• Hands-on experience with scan insertion and ATPG for stuck-at and At-Speed faults.
• Strong experience in scan coverage analysis and improvement.
• Hands-on MBIST insertion and simulation.
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.
• Experience with RTL and netlist-based DFT flows.
• Experience in DFT simulation with and without SDF.
• Working knowledge of Synthesis and Formal Verification tools.
• Experience in DC characterization.
• Experience generating TDL for ATE and supporting silicon/ATE bring-up.
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor.
• Good scripting skills in Perl and TCL.
• Exposure to STA is preferred.

Responsibilities

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams.
• Support DFT activities through tapeout and silicon bring-up.

Skills

Scan Insertion

ATPG for Stuck-at/At-Speed

Scan Coverage Analysis

MBIST Insertion & Simulation

Boundary Scan

TAP Controller

IEEE 1500/P1500

RTL DFT Flows

Netlist-based DFT

DFT Simulation w/ SDF

Synthesis & Formal Verification

DC Characterization

TDL for ATE

ATE Bring-up Support

DFT Tools (Synopsys, Cadence, Siemens/

Perl & TCL Scripting

STA Exposure Preferred

Education

BE/BTech/ME/MTech

Tools

Synopsys

Cadence

Siemens EDA/Mentor

Job description

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults
• Strong experience in scan coverage analysis and improvement
• Hands-on experience in MBIST insertion and simulation
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500
• Experience with RTL and netlist-based DFT flows
• Experience in DFT simulation with and without SDF
• Working knowledge of Synthesis and Formal Verification tools
• Experience in DC characterization
• Experience generating TDL for ATE and supporting silicon/ATE bring-up
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor
• Good scripting skills in Perl and TCL
• Exposure to Static Timing Analysis (STA) is preferred

Location:

Noida

Qualification:

BE/BTech/ME/MTech

Key Skills & Experience

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults
• Strong experience in scan coverage analysis and improvement
• Hands-on experience in MBIST insertion and simulation
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500
• Experience with RTL and netlist-based DFT flows
• Experience in DFT simulation with and without SDF
• Working knowledge of Synthesis and Formal Verification tools
• Experience in DC characterization
• Experience generating TDL for ATE and supporting silicon/ATE bring-up
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor
• Good scripting skills in Perl and TCL
• Exposure to Static Timing Analysis (STA) is preferred

Work

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows
• Work closely with Design, Verification, PD, STA, and ATE teams
• Support DFT activities through tapeout and silicon bring-up

Ideal Profile:

Strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up.