DFT Engineer | Noida | 5+

Erbity Private Limited; Dadri; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Erbity Private Limited in Noida is seeking a hands-on DFT engineer to drive scan insertion, ATPG generation, coverage closure and pattern validation across RTL and gate-level flows.

You will debug DFT, scan, ATPG and simulation issues, and collaborate with Design, Verification, PD, STA and ATE teams to support tapeout and silicon bring-up with strong scripting in Perl/TCL.

Qualifications

• Hands-on experience in scan insertion and ATPG for DFT.
• Strong knowledge of scan coverage analysis and improvements.
• Experience with MBIST insertion and simulation.
• Exposure to DFT tools from leading vendors and STA/ timing analysis is preferred.

Responsibilities

• Drive DFT insertion, ATPG generation, coverage closure and pattern validation.
• Debug DFT, scan, ATPG and simulation issues across RTL and gate-level flows.
• Collaborate with Design, Verification, PD, STA and ATE teams.
• Support tapeout and silicon bring-up activities.

Skills

Scan insertion

ATPG

Scan coverage analysis

MBIST insertion

Boundary Scan

TAP Controller

IEEE 1500/P1500

RTL DFT flows

DFT simulations

Scripting: Perl

Scripting: TCL

STA exposure

DC characterization

Tapeout support

Education

BE/BTech/ME/MTech in Electrical/EC

Tools

Synopsys DFT tools

Cadence tools

Siemens EDA/Mentor tools

Job description

Location: Noida

Qualification: BE/BTech/ME/MTech

Key Skills & Experience

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults.
• Strong experience in scan coverage analysis and improvement.
• Hands-on experience in MBIST insertion and simulation.
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.
• Experience with RTL and netlist-based DFT flows.
• Experience in DFT simulation with and without SDF.
• Working knowledge of Synthesis and Formal Verification tools.
• Experience in DC characterization.
• Experience generating TDL for ATE and supporting silicon/ATE bring-up.
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor.
• Good scripting skills in Perl and TCL.
• Exposure to Static Timing Analysis (STA) is preferred.

Work

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams.
• Support DFT activities through tapeout and silicon bring-up.

Ideal Profile: Strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up.