DFT Engineer

7Rays Semiconductors; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

7Rays Semiconductors in Bengaluru seeks a hands-on DFT/MBIST/SCAN engineer to lead MBIST insertion, ATPG pattern generation and simulations. You will execute BSCAN/MBIST tasks, run timing simulations (zero delay and SDF) and debug with GUI simulators (VCS/NCSim/Xcelium).

Expertise in fault models and shmoo analysis is required to drive test coverage and post-silicon activities. Strong scripting in Perl/Tcl is a plus; cross-functional collaboration with STA/PD teams and customer support will be a

Qualifications

• Clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts.
• Hands-on MBIST insertion, Scan Insertion, ATPG pattern generation and simulations.
• MBIST and BSCAN simulations using Cadence/Siemens Tessent/Synopsys.
• Experience with zero delay and SDF Timing Simulations.
• Good debugging skills using GUI mode of simulators like VCS, NCSim or Xcelium.
• Familiar with fault models: stuck-at, TDF, IDDQ and scan test coverage improvement techniques.
• SoC level DFT with OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan, post-silicon bring-up/production activities, tester debug with shmoo plots.
• Experience providing test mode timing constraints to STA and PD teams.
• Perl/Tcl scripting knowledge would be advantageous.

Responsibilities

• Hands-on MBIST insertion, Scan Insertion and ATPG pattern generation with simulations.
• Perform MBIST/BSCAN simulations using Cadence/Siemens Tessent/Synopsys tool suites.
• Work on zero delay as well as SDF timing simulations.
• Debug using GUI modes of VCS/NCSim/Xcelium.
• Handle fault models like stuck-at, TDF, IDDQ and improve scan test coverage.
• Contribute to SoC level DFT with OCC/OPCG insertion, EDT/Compression logic, clock module handling for scan and post-silicon activities.
• Provide test mode timing constraints to STA and PD teams.
• Possibly leverage Perl/Tcl scripting to automate flows.

Skills

BSCAN/MBIST/SCAN/ATPG concepts

MBIST insertion

Scan Insertion

ATPG pattern generation

Cadence Tessent

Siemens Tessent

Synopsys tools

VCS/NCSim/Xcelium debugging

fault models (stuck-at, TDF, IDDQ)

SoC DFT (OCC/OPCG)

shmoo plots & tester debugging

Perl/Tcl scripting

Tools

Cadence

Tessent

NCSim/Xcelium

Job description

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
• Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
• Candidate must have worked on zero delay as well as SDF Timing Simulations.
• Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
• The candidate should have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
• Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
• The candidate should have experience of providing test mode timing constraints to STA and PD teams.
• Additional knowledge of perl/tcl scripting will be an advantage.
• Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.