DFT Engineer | Noida | 5+

Erbity Private Limited; Ahmedabad District; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Erbity Private Limited is seeking a hands-on DFT engineer to drive scan insertion, ATPG, coverage closure, and silicon bring-up in Noida. The role requires experience with RTL and gate-level DFT flows, DFT simulations with/without SDF, and collaboration across Design, Verification, PD, and ATE teams.

The ideal candidate will be proficient with tools from Synopsys, Cadence, and Siemens EDA, and comfortable scripting in Perl/TCL. Excellent debugging skills and STA exposure are a plus.

Qualifications

• Ideal Profile: strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up.
• Bachelor level/masters in ECE/CS or related field preferred; strong background in DFT desirable.
• Experience with RTL and gate-level DFT flows and scripting for automation helpful.

Responsibilities

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams.
• Support DFT activities through tapeout and silicon bring-up.

Skills

Scan Insertion

ATPG

Scan Coverage Analysis

MBIST Insertion

Boundary Scan

TAP Controller

IEEE 1500/P1500

RTL DFT Flows

DFT Simulation (SDF)

Synthesis

Formal Verification

DC Characterization

ATE Bring-up

Perl

TCL

STA Exposure

Education

BE/BTech/ME/MTech

Tools

Synopsys

Cadence

Siemens EDA/Mentor

Job description

Location: Noida

Qualification: BE/BTech/ME/MTech

Key Skills & Experience

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults.
• Strong experience in scan coverage analysis and improvement.
• Hands-on experience in MBIST insertion and simulation.
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.
• Experience with RTL and netlist-based DFT flows.
• Experience in DFT simulation with and without SDF.
• Working knowledge of Synthesis and Formal Verification tools.
• Experience in DC characterization.
• Experience generating TDL for ATE and supporting silicon/ATE bring-up.
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor.
• Good scripting skills in Perl and TCL.
• Exposure to Static Timing Analysis (STA) is preferred.

Work

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams.
• Support DFT activities through tapeout and silicon bring-up.

Ideal Profile: Strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up.