DFT Engineer | Noida | 5+

Erbity Private Limited; Delhi; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Erbity Private Limited in Noida is looking for a hands-on DFT engineer with experience across scan insertion, ATPG, and coverage closure to support tapeout and silicon bring-up.

The role involves collaboration with Design, Verification, PD, STA, and ATE teams, plus DFT simulation, MBIST insertion, and boundary scan work in RTL and gate-level flows.

Qualifications

• Hands-on experience in Scan Insertion and ATPG for stuck-at and At-Speed faults.
• Strong experience in scan coverage analysis and improvement.
• Hands-on experience in MBIST insertion and simulation.
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.
• Experience with RTL and netlist-based DFT flows.
• Experience in DFT simulation with and without SDF.
• Working knowledge of Synthesis and Formal Verification tools.
• Experience in DC characterization.
• Experience generating TDL for ATE and supporting silicon/ATE bring-up.
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor.
• Good scripting skills in Perl and TCL.
• Exposure to Static Timing Analysis (STA) is preferred.

Responsibilities

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams.
• Support DFT activities through tapeout and silicon bring-up.

Skills

Scan Insertion

ATPG

Scan Coverage Analysis

MBIST Insertion

Boundary Scan

TAP Controller

IEEE 1500 / P1500

RTL DFT Flows

Netlist-based DFT Flows

DFT Simulation

Synthesis

Formal Verification Tools

DC Characterization

TDL for ATE

Silicon/ATE Bring-up

DFT Tools (Synopsys, Cadence, Siemens/

Perl

TCL

Static Timing Analysis

Education

BE/BTech/ME/MTech

Tools

Synopsys

Cadence

Siemens EDA / Mentor

Perl

TCL

Job description

Location: Noida

Qualification: BE/BTech/ME/MTech

Key Skills & Experience

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults.
• Strong experience in scan coverage analysis and improvement.
• Hands-on experience in MBIST insertion and simulation.
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.
• Experience with RTL and netlist-based DFT flows.
• Experience in DFT simulation with and without SDF.
• Working knowledge of Synthesis and Formal Verification tools.
• Experience in DC characterization.
• Experience generating TDL for ATE and supporting silicon/ATE bring-up.
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor.
• Good scripting skills in Perl and TCL.
• Exposure to Static Timing Analysis (STA) is preferred.

Work

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams.
• Support DFT activities through tapeout and silicon bring-up.

Ideal Profile: Strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up.