DFT Engineer | Noida | 5+

Erbity; Delhi; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Erbity in Noida, India seeks a hands-on DFT engineer to drive insertion, ATPG, coverage closure and pattern validation across RTL and gate-level flows.

You will debug DFT/ATPG issues, collaborate with Design, Verification, PD, STA, and ATE teams, and support tapeout and silicon bring-up. BE/BTech/ME/MTech holders with scan/MBIST/STA preferred.

Qualifications

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults.
• Strong experience in scan coverage analysis and improvement.
• Experience with MBIST insertion and simulation.
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.
• Experience with RTL and netlist-based DFT flows.
• Experience in DFT simulation with and without SDF.
• Working knowledge of Synthesis and Formal Verification tools.
• Experience in DC characterization.
• Experience generating TDL for ATE and supporting silicon/ATE bring-up.
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor.
• Good scripting skills in Perl and TCL.
• Exposure to Static Timing Analysis (STA) is preferred.

Responsibilities

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation.
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows.
• Work closely with Design, Verification, PD, STA, and ATE teams.
• Support DFT activities through tapeout and silicon bring-up.

Skills

Scan Insertion

ATPG

Stuck-at fault

At-Speed faults

Scan coverage

MBIST insertion

MBIST simulation

Boundary Scan

TAP Controller

IEEE 1500/P1500

RTL DFT flows

netlist-based DFT flows

DFT simulation with/without SDF

Synthesis

Formal Verification tools

DC characterization

TDL for ATE

ATE bring-up

Perl scripting

TCL scripting

STA awareness

Education

BE/BTech/ME/MTech

Tools

Synopsys tools

Cadence tools

Siemens EDA/Mentor

Perl

TCL

Job description

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults
• Strong experience in scan coverage analysis and improvement
• Hands-on experience in MBIST insertion and simulation
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500
• Experience with RTL and netlist-based DFT flows
• Experience in DFT simulation with and without SDF
• Working knowledge of Synthesis and Formal Verification tools
• Experience in DC characterization
• Experience generating TDL for ATE and supporting silicon/ATE bring-up
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor
• Good scripting skills in Perl and TCL
• Exposure to Static Timing Analysis (STA) is preferred

Location:

Noida

Qualification:

BE/BTech/ME/MTech

Key Skills & Experience

• Hands-on experience in Scan Insertion and ATPG for Stuck-at and At-Speed faults
• Strong experience in scan coverage analysis and improvement
• Hands-on experience in MBIST insertion and simulation
• Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500
• Experience with RTL and netlist-based DFT flows
• Experience in DFT simulation with and without SDF
• Working knowledge of Synthesis and Formal Verification tools
• Experience in DC characterization
• Experience generating TDL for ATE and supporting silicon/ATE bring-up
• Exposure to DFT tools from Synopsys, Cadence, and Siemens EDA/Mentor
• Good scripting skills in Perl and TCL
• Exposure to Static Timing Analysis (STA) is preferred

Work

• Drive DFT insertion, ATPG generation, coverage closure, and pattern validation
• Debug DFT, scan, ATPG, and simulation issues across RTL and gate-level flows
• Work closely with Design, Verification, PD, STA, and ATE teams
• Support DFT activities through tapeout and silicon bring-up

Ideal Profile:

Strong hands-on DFT engineer with end-to-end exposure from scan insertion and ATPG through coverage closure and ATE bring-up.