DFT Engineer

Kairos Technologies; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Kairos Technologies in Bengaluru, India is seeking a Lead DFT Engineer to drive design-for-test across complex SoCs. You will own DFT architecture, implementation, and sign-off with a strong focus on Scan Insertion, MBIST, and ATPG to ensure high silicon quality and optimal test coverage.

The ideal candidate has 6–12 years of hands-on DFT experience, deep knowledge of scan, MBIST, ATPG, and familiarity with Tessent and TestMAX tools, plus scripting in TCL/Python for flow automation.

Qualifications

• 6–12 years of hands-on DFT experience.
• Strong expertise in Scan Insertion and scan architecture.
• MBIST implementation for memories and repair flows.
• ATPG generation, fault simulation, and coverage optimization.
• DFT validation, gate‑level sim, and debug.
• Proficiency with DFT tools (Tessent/TestMAX/DFT Compiler) and scripting.

Responsibilities

• Define and implement DFT architecture for complex SoCs and IPs.
• Drive Scan Insertion, scan compression, and scan verification.
• Develop and integrate MBIST solutions for memories and repair flows.
• Generate and optimize ATPG patterns for various fault models.
• Perform DFT verification, coverage analysis, and debugging.
• Collaborate with RTL, PD, STA, and Test Eng to achieve DFT closure.
• Drive DFT sign-off and improve test coverage and silicon quality.
• Develop automation scripts to improve DFT productivity.

Skills

DFT

ATPG

Scripting (Python/TCL)

Education

B.E./B.Tech in Electronics/EEE/CS or related

Tools

Siemens Tessent

Synopsys TestMAX

DFT Compiler

Job description

DFT Lead:

Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, or a related discipline.
• Location Bangalore
• Experience: 6-12 Years
• Notice Period Immediate to 90 Days

About the Role

We are looking for a Lead DFT Engineer to drive Design-for-Test implementation for complex SoCs across advanced technology nodes. You will own DFT architecture, implementation, and sign-off with a strong focus on Scan Insertion, MBIST, and ATPG, enabling high-quality silicon with optimal test coverage.

What You'll Do

• Define and implement DFT architecture for complex SoCs and IPs.
• Drive Scan Insertion, scan compression, scan stitching, and scan verification.
• Develop and integrate MBIST solutions for embedded memories and memory repair flows.
• Generate and optimize ATPG patterns for stuck-at, transition, and advanced fault models.
• Perform DFT verification, coverage analysis, pattern validation, and debug.
• Collaborate with RTL, Physical Design, STA, and Test Engineering teams to achieve DFT closure.
• Drive DFT sign-off, improve test coverage, and optimize test time and silicon quality.
• Develop automation scripts to improve DFT productivity and flow efficiency.

What We’re Looking For

• 6-12 years of hands-on experience in Design for Test ( DFT ).
• Strong expertise in Scan Insertion, scan compression, and scan architecture.
• Deep experience with MBIST implementation, integration, and verification.
• Strong knowledge of ATPG generation, fault simulation, and coverage optimization.
• Hands‑on experience with industry‑standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, or equivalent.
• Understanding of JTAG/IEEE 1149.1, boundary scan, and IEEE 1500 standards.
• Experience with DFT validation, gate‑level simulation, and scan debug.
• Proficiency in TCL, Python, or Perl scripting for flow automation.
• Excellent debugging, analytical, and cross‑functional collaboration skills.