Design and Verification Engineer

Metavlsi Technologies; Bengaluru; On-site; INR 1,400,000 - 2,600,000; Full time

Benefits offered by this job

Work from Office

Job summary

MetaVLSI Technologies in Bangalore seeks a SoC Verification Engineer with 4–12 years of independent IP DV experience. You will own verification tasks, create testplans, build testbenches and DV infrastructure using standard DV methodologies.

This is a work-from-office role requiring hands-on debugging and cross-functional collaboration across geo locations. The ideal candidate has strong experience in AXI/PCIe/UCIe, UVM, SystemVerilog, and SystemC-based verification, and can drive IP DV projects

Qualifications

• Experience level: 4 to 12 years with IP DV ownership.
• Independent verification ownership across IP DV.
• Hands-on verification including testplan creation and DV infrastructure.

Responsibilities

• Domain: AXI, PCIe, UCIe protocol experience is highly preferred.
• Develop test benches for IP/Subsystems/SoC.
• Execute verification of SoC/Sub-Systems/IP DV.
• Lead IP DV projects with technical guidance and debugging expertise.
• Proficient with UVM/SystemVerilog/CDV/MDV and DV signoffs.
• Capable of hybrid test benches (SV, SystemC, Python).

Skills

Independent verification

Testbench development

DV methodology

UVM

SystemVerilog

CDV/MDV

DV signoffs

AXI/PCIe/UCIe

Tools

SystemVerilog

SystemC

Python

Job description

Job Title:[SoC Verification Engineer]

Company: MetaVLSI Technologies

Location: Bangalore

Experience: [4-12 Years]

Note:[Work from Office]

Preferred: [Immediate Candidate

Job Description

• Experience level: 4 to 12 years Independent Verification Ownership of IP DV.
• Collaborating with various cross functional teams at multiple geo locations as part of execution.
• Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts)

Role and Responsibilities:

• Domain: AXI, PCIe, UCIe protocol experience is highly preferred
• Must have experience in developing test benches for IP/Subsystems/SoC.
• In depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV.
• Previous experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities.
• Strong hands on experience with common verification tools and methodology including UVM/ System Verilog/CDV/MDV, DV signoffs.
• Must have a strong domain expertise in one or more following areas - AXI/PCIe/UCIe.
• Experience in Hybrid test benches (SV, SystemC, Python) and SystemC based reference model test vectors/stimulus based verification is desirable.