Design and Verification Engineer

Lancesoft; Hyderabad, Chennai District, Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Lancesoft is seeking a Design Verification Engineer to drive DV for IP, subsystem, or SoC-level verification with emphasis on DDR, PCIe, UCIe and USB protocols. Proficiency in SystemVerilog, UVM, testbench development, assertions, and coverage closure is required.

Applicants will engage in protocol-level verification, debugging, regression analysis, and issue tracking, collaborating with RTL and architecture teams to ensure robust silicon validation.

Qualifications

• 3+ years of experience in Design Verification for IP, subsystem, or SoC-level verification.
• Strong experience in verification of high-speed protocols such as DDR, PCIe, UCIe, and USB.
• Hands-on experience with SystemVerilog and UVM methodology.
• Solid understanding of functional verification, testbench development, test-case creation, assertions, and coverage closure.
• Experience in protocol-level verification, debugging, regression analysis, and issue tracking.
• Knowledge of Functional Coverage and Code Coverage with coverage closure.

Responsibilities

• Design and develop verification environments for IP, subsystem, or SoC blocks.
• Verify high-speed interfaces and protocols (DDR, PCIe, UCIe, USB) to ensure correctness.
• Create and run test benches, write assertions, and drive coverage closure.
• Debug failures, analyze regressions, and coordinate with RTL/design teams.

Skills

Design Verification

DV

DDR

PCIe

UCIe

USB

SystemVerilog

UVM

functional verification

testbench development

assertions

coverage closure

protocol-level verification

debugging

regression analysis

SVA

GLS

RTL concepts

SoC/IP integration

VCS

Xcelium

Questa/ModelSim

Verdi

Python

Perl

Shell

Tcl

Tools

VCS

Xcelium

Questa/ModelSim

Verdi

Job description

Design Verification Engineer DDR / PCIe / UCIe / USB / GLS

Experience: 3+ Years
Location: Bangalore / Hyderabad / Noida/Chennai
Notice Period: Immediate to 30 Days preferred

Job Description:

• 3+ years of experience in Design Verification (DV) for IP, subsystem, or SoC-level verification.


• Strong experience in verification of high-speed protocols such as DDR, PCIe, UCIe, and USB.


• Hands-on experience with SystemVerilog and UVM methodology.


• Strong understanding of functional verification, testbench development, test-case creation, assertions, and coverage closure.


• Experience in protocol-level verification, debugging, regression analysis, and issue tracking.


• Good knowledge of Functional Coverage and Code Coverage with experience in coverage closure.


• Experience with SVA (SystemVerilog Assertions) and constrained-random verification.


• Exposure to GLS (Gate-Level Simulation), including SDF simulation, timing checks, X-propagation, and post-layout verification.


• Good understanding of RTL design concepts, digital logic, and SoC/IP integration.


• Hands-on experience with simulation and debug tools such as VCS, Xcelium, Questa/ModelSim, Verdi, or equivalent.


• Strong scripting/programming skills in Python, Perl, Shell, or Tcl.


• Ability to analyze failures, debug complex issues, and work closely with RTL, design, and architecture teams.