SoC Verification Lead

ACL Digital; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

ACL Digital is seeking an experienced Design Verification Engineer in Bengaluru, Karnataka. The candidate will drive verification activities at the IP and SoC levels, define strategies, and mentor junior engineers. Responsibilities include developing UVM/SystemVerilog environments and leading complex projects. Ideal candidates will have strong skills in SystemVerilog, UVM, high-speed protocols, and a BE/B.Tech/MS in a related field. The company offers a dynamic work environment and growth opportunities.

Qualifications

• Strong hands-on experience in SystemVerilog, UVM, and SVA.
• Expertise in IP and SoC level verification.
• Experience with high-speed protocols like Ethernet, USB, DDR/LPDDR.
• Experience in low-power verification (UPF/CPF) is a plus.

Responsibilities

• Define and execute verification plans and methodologies for IP and SoC level designs.
• Develop scalable UVM/SystemVerilog based verification environments from scratch.
• Lead testbench architecture, stimulus creation, scoreboards, assertions, and functional coverage.
• Drive verification closure including coverage analysis, regressions, and sign-off metrics.

Skills

SystemVerilog

UVM

SVA

High-speed protocols

Coverage-driven verification

Debug skills

VIP integration

Education

BE / B.Tech / MS in Electronics / Electrical / VLSI

Tools

VCS

Xcelium

Questa

Job description

We are looking for an experienced Design Verification Engineer with strong expertise in IP/Sub-system/SoC level verification and high-speed protocols. The candidate will be responsible for driving end-to-end verification activities, defining verification strategies, and leading complex verification closures.

Key Responsibilities

• Define and execute verification plans and methodologies for IP and SoC level designs.
• Develop scalable UVM/SystemVerilog based verification environments from scratch.
• Lead testbench architecture, stimulus creation, scoreboards, assertions, and functional coverage.
• Drive verification closure including coverage analysis, regressions, and sign-off metrics.
• Work closely with design, architecture, and firmware teams for feature validation and debug.
• Handle complex debug at RTL, gate level, and emulation/prototyping platforms.
• Mentor junior engineers and contribute to methodology improvements.

Required Technical Skills

• Strong hands-on experience in SystemVerilog, UVM, and SVA.
• Expertise in IP and SoC level verification.
• Experience with one or more high-speed protocols, such as:
• Ethernet
• USB
• DDR/LPDDR
• Experience with VIP integration and customization.
• Proficiency in debug using industry-standard simulators (VCS / Xcelium / Questa).
• Strong understanding of coverage-driven verification and constrained random methodology.
• Experience in low-power verification (UPF/CPF) is a plus.
• Exposure to emulation or FPGA prototyping is an added advantage.

Soft Skills

• Proven ability to lead verification efforts for complex projects.
• Strong problem-solving and debugging skills.
• Excellent communication and cross-functional collaboration.

Education

• BE / B.Tech / MS in Electronics / Electrical / VLSI / related field.

Nice to Have

• Experience in multi-core SoC / cache coherency verification
• Scripting knowledge in Python/Perl/Shell/TCL