Senior Design Verification Engineer

Sunrise Biztech Systems; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Sunrise Biztech Systems in Bengaluru seeks a Verification Engineer with 6–12 years of experience to lead ASP/SoC verification efforts. The role focuses on developing verification plans, building IP‑level environments with SystemVerilog and UVM, and creating robust test scenarios.

You will verify AXI4/AXI4-Lite/AXI-Stream protocols and integrate AI tools to enhance productivity. Responsibilities include regression triage, debugging RTL and testbenches, and collaborating with design and firmware

Qualifications

• Experience in ASIC/SoC verification is required.
• Strong experience with SystemVerilog and UVM.
• Experience in IP/SoC verification and protocol checks.

Responsibilities

• Develop detailed verification plans based on design specifications.
• Build reusable IP-level verification environments using SystemVerilog and UVM.
• Create directed, constrained-random, and stress test scenarios.
• Perform functional, code, assertion, and coverage analysis and closure.
• Verify AXI4, AXI4-Lite, and AXI-Stream protocols.
• Develop protocol checkers, assertions, scoreboards, and coverage models.
• Triage regressions and analyze root causes of failures.
• Debug RTL, UVM environments, assertions, testbenches, waveforms, and logs.
• Collaborate with design, firmware, and architecture teams to resolve issues.
• Track and communicate verification and debug status.
• Support verification sign-off for complex IP and SoC subsystems.
• Utilize AI tools for test generation, UVM coding, and debugging productivity.

Skills

SystemVerilog

UVM

AXI4

AXI4-Lite

AXI-Stream

Testbenches

Tools

Copilot

ChatGPT

Claude

Gemini

Job description

Position:

Verification Engineer

Experience:

6-12 Years

Location:

Bangalore

Contract:

12 Months

Role & responsibilities

• Develop detailed verification plans based on design and architecture specifications
• Build reusable and scalable IP-level verification environments using SystemVerilog and UVM
• Create and execute directed, constrained-random, and stress test scenarios
• Perform functional, code, assertion, and toggle coverage analysis and closure
• Verify AXI4, AXI4-Lite, and AXI-Stream protocols
• Develop protocol checkers, assertions, scoreboards, and coverage models
• Perform regression triaging and root-cause analysis of failures
• Debug RTL, UVM environments, assertions, testbenches, waveforms, and logs
• Collaborate with design, firmware, and architecture teams to resolve issues
• Track and communicate verification and debug status
• Support verification sign-off for complex IP and SoC subsystems
• Utilize AI tools such as Copilot, ChatGPT, Claude, Gemini, or equivalent for test generation, UVM coding, documentation, regression analysis, and debug productivity
• Apply prompt engineering and AI-assisted automation techniques to improve verification workflows