Design Verification (DV) Engineer

Gtc Informatics Private Limited; India; Remote; INR 1,200,000 - 2,400,000; Full time

Job summary

GTC Informatics Private Limited is seeking experienced Design Verification Engineers for ASIC and SoC verification projects across India. These roles are open on both full-time and contract basis, depending on client and project requirements. Experienced candidates who can join quickly are encouraged to apply.

Location: PAN INDIA. You will build verification plans and testbenches, write test cases and coverage models, run regressions, debug issues, and work with RTL design teams to deliver

Qualifications

• 4–10 years of experience in ASIC/SoC design verification.
• Hands-on SystemVerilog and UVM experience.
• Experience with assertions (SVA) and coverage.
• Experience with PCIe, AXI, AHB, APB, DDR, USB or Ethernet.
• Proficient with simulators VCS/Questa/Xcelium.
• Good debugging and communication skills.

Responsibilities

• Build verification plans and testbenches using SystemVerilog and UVM.
• Write test cases, sequences, checkers, scoreboards and coverage models.
• Run regressions, debug failures and work with RTL design teams to fix issues.
• Drive functional and code coverage closure.
• Verify IP, subsystem and SoC-level designs.
• Work closely with design and architecture teams on client projects.

Skills

SystemVerilog

UVM

Testbench development

Debugging

Communication

Tools

VCS

Questa

Xcelium

Job description

GTC Informatics Private Limited is hiring experienced Design Verification Engineers for ASIC and SoC verification projects across India. These positions are open on both a full-time and contract basis, depending on client and project requirements. Experienced candidates who can join quickly are encouraged to apply.

Location : PAN INDIA

Roles & Responsibilities:

• Build verification plans and testbenches using SystemVerilog and UVM
• Write test cases, sequences, checkers, scoreboards and coverage models
• Run regressions, debug failures and work with RTL design teams to fix issues
• Drive functional and code coverage closure
• Verify IP, subsystem and SoC-level designs
• Work closely with design and architecture teams on client projects

Required Skills & Experience:

• 4–10 years of experience in ASIC/SoC design verification
• Strong hands‑on skills in SystemVerilog and UVM
• Experience writing assertions (SVA) and coverage
• Experience with protocols such as PCIe, AXI, AHB, APB, DDR, USB or Ethernet
• Hands‑on with simulators such as VCS, Questa or Xcelium
• Good debugging and communication skills

Good to Have:

• PCIe protocol verification experience
• Exposure to formal verification
• ing skills in Python, Perl or Shell