Design verification Lead Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru seeks a hands-on verification engineer to drive IP/Subsystem/SoC DV.

Collaborate across geos, develop test plans, build testbenches, and automate coverage/regression using UVM/SystemVerilog and SystemC/Python.

Candidates should have AXI/PCIe/UCIe domain expertise and strong debugging and leadership skills.

Qualifications

• Must have experience developing test benches for IP/Subsystems/SoC.
• In-depth knowledge and hands-on verification of SoC/Sub System/IP DV.
• Independently drive IP DV projects; lead a team; debugging; SoC architecture understanding.

Responsibilities

• Collaborate with cross-functional teams at multiple geographies as part of execution.
• Work hands-on to close all verification aspects: testplan creation, building testbenches based on DV methodology, developing DV infrastructure (coverage/regression/simulation scripts).
• Contribute to DV signoffs and maintain rigorous verification standards.

Skills

Testbench development

DV project leadership

SoC/IP verification

UVM/SystemVerilog

DV methodologies (CDV/MDV)

Tools

UVM

SystemVerilog

SystemC

Python

Job description

Role and Responsibilities

Collaborating with various cross functional teams at multiple geo locations as part of execution.

Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts)

Domain

AXI, PCIe, UCIe protocol experience is highly preferred

• Must have experience in developing test benches for IP/Subsystems/SoC.
• In depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV.
• Previous experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities.
• Strong hands on experience with common verification tools and methodology including UVM/ System Verilog/CDV/MDV, DV signoffs.
• Must have a strong domain expertise in one or more following areas - AXI/PCIe/UCIe.
• Experience in Hybrid test benches (SV, SystemC, Python) and SystemC based reference model test vectors/stimulus based verification is desirable.