Senior Design Verification Engineer

ThunderSoft India Private Limited; Bengaluru; Sur place; INR 1 500 000 - 2 300 000; Plein temps

Résumé du poste

ThunderSoft India Private Limited is seeking an experienced verification engineer to drive IP DV for AXI/PCIe/UCIe domains. You will develop test benches for IPs, subsystems, and SoCs, and lead DV projects with hands-on debugging and architecture understanding.

The role requires strong SystemVerilog/UVM experience, DV signoffs, and proficiency with SystemC and Python in hybrid bench environments. Collaboration with a cross-functional team to ensure robust verification is essential.

Qualifications

• Experience in developing test benches for IPs, subsystems or SoCs.
• Hands-on verification of SoC/Sub System/IP DV with depth and rigor.
• Proven track record independently driving IP DV projects and guiding teams.
• Strong hands-on with verification tools and methods: UVM, SystemVerilog, CDV/MDV, DV signoffs.
• Expertise in AXI, PCIe or UCIe domains.
• Desirable: Hybrid test benches (SV, SystemC, Python) and SystemC reference models.

Responsabilités

• Develop and maintain test benches for IPs, subsystems and SoCs.
• Execute verification of DV for SoCs and subsystems with rigor.
• Lead IP DV projects, provide technical guidance, and participate in debugging and architecture reviews.
• Apply UVM/SystemVerilog-based methodologies and ensure DV signoffs are achieved.
• Leverage domain expertise in AXI/PCIe/UCIe to drive verification strategies.
• Work with hybrid benches (SV/SystemC/Python) and model-based test vectors.

Connaissances

AXI

PCIe

UCIe

Test Benches

SystemVerilog

UVM

DV Signoffs

SystemC

Python

Outils

SystemC

Python

Description du poste

Role and Responsibilities:

Domain: AXI, PCIe, UCIe protocol experience is highly preferred

1. Must have experience in developing test benches for IP/Subsystems/SoC.

2. In depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV.

3. Previous experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities.

4. Strong hands on experience with common verification tools and methodology including UVM/ System Verilog/CDV/MDV, DV signoffs.

5. Must have a strong domain expertise in one or more following areas - AXI/PCIe/UCIe.

6. Experience in Hybrid test benches (SV, SystemC, Python) and SystemC based reference model test vectors/stimulus based verification is desirable.