Lead Engineer - SoC Design Verification

NXP Semiconductors; Maharashtra; On-site; INR 3,000,000 - 5,200,000; Full time

Job summary

NXP Semiconductors in Pune seeks a Senior Design Verification Engineer with 6+ years of experience to execute complex SoC verification. The role focuses on ARM-based microcontrollers, low‑power verification, and multi‑IP interfaces in a fast‑paced environment.

You will develop and own verification suites, create test cases, run UVM simulations, and drive DV closure across IPs while mentoring juniors.

Qualifications

• 5–12 years of SoC/IP verification with tape‑outs experience.
• Strong expertise in ARM-based microcontrollers and SoC verification.
• Proficiency in Verilog, SystemVerilog, UVM and constrained‑random verification.
• Familiarity with EDA tools: VCS, Xcelium.
• Low‑power verification (UPF) a plus.
• Gate‑level and power‑aware simulations a plus.
• Good knowledge of assertions (SVA) and functional coverage.
• Verification of multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI.
• Experience with security IPs and Flash memory is nice to have.
• Experience with Analog IPs (ADC, DAC, PLLs) is a plus.

Responsibilities

• Develop and own SoC‑level and/or IP‑level verification suites with coverage goals.
• Execute verification plan per product specs defined by architects.
• Develop, debug and run UVM verification environment for RTL/netlist simulation.
• Define and develop test cases; create stimulus and assertions; run simulation and analyze coverage.
• Drive DV closure on diverse IPs and subsystems for maximum coverage and quality.
• Collaborate with the team to improve flows for maximum reuse and efficiency.
• Mentor junior team members and collaborate with design teams for issue resolution and sign‑off.

Skills

ARM-based verification

Verilog / SystemVerilog / UVM

EDA tools: VCS / Xcelium

Low-power verification (UPF)

Gate-level / power-aware sim

Assertions (SVA)

Interfaces: SPI, I2C, UART, USB, PCIe,

Flash memory & Security IPs

Analog IPs: ADC, DAC, PLLs

Fast-paced environment

Team player / communication

Education

Bachelor's/Master’s in Microelectronics/ Electronics/ Electrical Engineering

Tools

N/A

Job description

Job Title: Senior Design Verification Engineer / Location: Pune

We are seeking an experienced Design Verification Engineer with 6+ years of expertise for execution of complex SoCs. The ideal candidate will have deep knowledge of ARM-based microcontrollers, low‑power design verification, and experience with multiple interfaces and security IPs. This is a hands‑on role requiring strong technical skills and collaboration in a fast‑paced environment.

Key Responsibilities

• Develop and own SoC‑level and/or IP‑level verification suites with coverage goals.
• Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
• Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.
• Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.
• Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
• Familiar with both SoC‑level and IP‑level verification environments.
• Collaborate with the team in developing and improving flows for maximum reuse and efficiency.
• Mentor junior team members while actively collaborating with design teams for issue resolution and sign‑off.

Required Qualifications

• Experience: 5-12 years in SoC/IP verification with participation in successful tape‑outs of SoCs.
• Technical Skills:
  • Strong expertise in ARM-based microcontrollers and SoC‑level verification, including C based DV.
  • Proficiency in Verilog, SystemVerilog, UVM, and constrained‑random verification.
  • Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium).
  • Experience with low‑power verification (UPF) is a plus.
  • Gate‑level simulations and power‑aware simulations is a plus.
  • Good working knowledge of assertions (SVA) and functional coverage.
  • Verification of multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI is desirable.
  • Knowledge of Flash memory and security IPs is nice to have.
  • Any experience with common Analog IPs in microcontroller design (ADC, DAC, PLLs) is an added advantage.
• Soft Skills:
  • Comfortable working in a fast‑paced environment.
  • Strong team player with excellent communication skills.
• Education: Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering