Senior Design Verification Engineer

Allegis Group; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Allegis Group in Bangalore seeks an experienced Senior Design Verification Engineer to join a high-performance verification team working on advanced IP/SoC verification projects.

Responsibilities include SystemVerilog/UVM verification, AXI protocol checks, and regression triaging with a focus on AI-assisted productivity and sign-off of verification results.

Qualifications

• SystemVerilog and UVM experience for IP verification.
• AXI4/AXI4-Lite/AXI-Stream protocol verification.
• Regression triaging and root-cause analysis.
• Functional coverage, assertions, scoreboards and checkers.
• RTL debug, waveform analysis and verification sign-off.

Responsibilities

• Develop reusable UVM-based verification environments.
• Create directed and constrained-random test scenarios.
• Drive code, functional, assertion, and toggle coverage closure.
• Perform regression triaging and debug complex failures.
• Verify AXI and PCIe-based IPs/subsystems.
• Collaborate with Design, Firmware, and Architecture teams.
• Utilize AI-driven solutions to improve verification productivity.

Skills

SystemVerilog & UVM

AXI Protocol Verification

Regression Triaging

Functional Coverage

RTL Debug & Waveforms

Tools

PCIe Gen3/Gen4/Gen5

Copilot

ChatGPT

Job description

Hiring: Senior Design Verification Engineer | Bangalore | 5-12 Years

We are looking for an experienced Senior Design Verification Engineer to join Product company a high-performance verification team working on advanced IP/SoC verification projects.

Mandatory Skills

SystemVerilog & UVM with strong IP Verification experience
AXI Protocol Verification (AXI4/AXI4-Lite/AXI-Stream)
Regression Triaging & Root Cause Analysis
Functional Coverage, Assertions, Scoreboards, Checkers
RTL Debug, Waveform Analysis, Verification Sign-off

Good to Have

PCIe Gen3/Gen4/Gen5 Verification
Experience with AI tools such as Copilot, ChatGPT, Claude, Gemini
Verification Automation & Prompt Engineering

Key Responsibilities

• Develop reusable UVM-based verification environments.
• Create directed and constrained-random test scenarios.
• Drive code, functional, assertion, and toggle coverage closure.
• Perform regression triaging and debug complex failures.
• Verify AXI and PCIe-based IPs/subsystems.
• Collaborate closely with Design, Firmware, and Architecture teams.
• Utilize AI-driven solutions to improve verification productivity and debug efficiency.

Experience

5-12 Years

Location

Bangalore

Notice Period

Immediate to 30 Days Preferred