Sr Analog Mixed Signal Verification Engineer - UK

microTECH Global Ltd; Scotland; On-site; GBP 50,000 - 70,000; Full time

Job summary

A leading technology firm in Edinburgh is seeking a Senior Analog Mixed Signal Verification Engineer. The role involves implementing chip-level mixed signal simulations and producing verification plans. Candidates should have over 5 years of AMS verification experience and a Bachelor's degree in Electrical or Electronic Engineering. Excellent communication skills are essential, along with knowledge of both analog and digital design fundamentals. The position is permanent and based in the UK.

Qualifications

• At least 5 years of experience in AMS verification.
• Excellent written and verbal communication skills.
• Knowledgeable in both analog and digital design fundamentals.

Responsibilities

• Implement chip-level mixed signal simulation environments.
• Produce AMS Verification Plan.
• Develop chip-level self-checking models.

Skills

AMS verification

Cadence AMS designer

Verilog-AMS

Spectre simulator

Tcl scripting

Python scripting

Education

Bachelor's degree in Electrical/Electronic Engineering

Tools

Cadence tools

Job description

Job Title : Sr Analog Mixed Signal Verification Engineer

Location : Edinburgh, UK

Job Type : Permanent

Role overview

We are seeking a Senior Analog Mixed Signal verification engineer to join my client’s expanding Design Centre in Edinburgh, Scotland. Critical to their new product development plans, the Centre designs advanced power control IC's for a broad range of product applications. My client is recognised world-wide as providing state-of-the-art automotive power integrated circuits. You will be part of a new verification team which collaborates on the mixed-signal verification of gate-driver ICs and embedded SoCs based on innovative new core architectures.

Responsibilities

• Implementation of chip-level mixed signal simulation environments
• Production of AMS Verification Plan
• Develop chip-level self-checking models.
• Chip top-level verification sign-off ahead of first silicon tapeout
• Coordinate verification responsibilities with Digital and Analog Design / Verification teams.
• Maintenance and continuous improvement of verification methodology, automation and regression control.

Key Relationships

Internal

• Collaborate with digital design and verification engineers.
• Collaborate with analog design engineers.
• Collaborate on requirements and test definition in Jama with the wider team.

External

• Liaise with off-site design teams as required.
• Communicate with EDA and tool vendors.

Requirements

• Possess at least a Bachelors degree in Electrical and / or Electronic Engineering or equivalent.
• Must have excellent written and verbal communication skills.
• Should have at least 5 years of experience in AMS verification
• Must be knowledgeable in both analog and digital design fundamentals.

Desirable

• Experience of SystemVerilog Assertions.
• Knowledge of UVM-MS concepts
• Some scripting knowledge (e.g. Tcl, Python, POSIX shell).
• Jama (or equivalent)

Skills, Knowledge and Aptitudes

• Cadence AMS designer (Maestro / CLIPS)
• Verilog-AMS
• Hierarchy Editor configuration
• Custom connect modules and connect rules and / or IE cards
• Spectre / APS simulator or Mentor equivalent.
• Real-Number Modeling : wreal, SV

If you are interested and suited, please