Senior Design Engineer – Hybrid Space RTL/FPGA

AccelerComm Ltd; Cambridge; Hybrid; GBP 90,000 - 130,000; Full time

Benefits offered by this job

EMI share options

Pension

Private health insurance

Flexible working hours

Hybrid working

Bonus up to 20%

Job summary

AccelerComm Ltd in Cambridge is seeking Senior Design Engineers to develop RTL for non-terrestrial communications hardware, aiming to deploy a space-qualified 5G base station on satellites. You will contribute to RTL design, testbench creation, and deployment on FPGA/ASIC platforms, collaborating with Algorithm and System Architecture teams.

The role emphasizes timing, power management, and high-speed interfaces, with hybrid working and opportunities to influence the full design lifecycle.

Qualifications

• Essential: Expert knowledge of RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products.
• Essential: Strong skillset delivering digital designs in the ASIC and FPGA industry.
• Essential: Optimisation of timing and hardware resources for high throughput data or signal processing; experience in power management, synthesis and timing analysis.
• Essential: Track record collaborating across teams to produce integrated solutions.
• Essential: Experience in technical documentation writing – design specifications, user guides, verification plans.
• Essential: Expert user of EDA tools for simulation and synthesis.
• Desirable: Knowledge of communications signal processing algorithms (e.g., ECC, equalisation, channel estimation, beamforming).
• Desirable: Familiarity with AMBA bus protocols.
• Desirable: Understanding of UVM verification techniques or practical UVM IP verification.
• Desirable: Experience with C++/SystemC for design modelling and integration.
• Desirable: Experience with high-speed interfaces such as PCI-E or JESD.
• Desirable: Knowledge of Python scripting.
• Desirable: Knowledge of project methodologies across the design lifecycle (agile, waterfall) and traceability.
• Desirable: Experience with AMD FPGAs and associated design tools or ASIC backend tools.

Responsibilities

• Work closely with the Algorithm and System Architecture teams to translate requirements into micro-architectures for RTL implementations.
• Implement designs targeting FPGA and ASIC using industry-standard techniques, including testbench creation.
• Deploy designs onto FPGA development platforms for validation and system integration.
• Adhere to AccelerComm engineering methodology and design techniques; propose improvements to flow and product quality.
• Collaborate across design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC/FPGA.

Skills

RTL Verilog/SystemVerilog

ASIC/FPGA design

Timing optimization

Power management

Technical documentation

EDA tools

C++/SystemC modeling

UVM verification

PCI-E/JESD interfaces

Python scripting

AMBA protocols

Project methodologies (Agile/Waterfall

Job description

AccelerComm Ltd in Cambridge is seeking Senior Design Engineers to develop RTL for non-terrestrial communications hardware, aiming to deploy a space-qualified 5G base station on satellites. You will contribute to RTL design, testbench creation, and deployment on FPGA/ASIC platforms, collaborating with Algorithm and System Architecture teams.

The role emphasizes timing, power management, and high-speed interfaces, with hybrid working and opportunities to influence the full design lifecycle.