Lead Hardware Design Architect (FPGA/ASIC) — Hybrid

AccelerComm Ltd; Cambridge; Hybrid; GBP 90,000 - 130,000; Full time

Benefits offered by this job

Bonus up to 20% salary

EMI share options

Pension

Private health insurance

Hybrid working

Job summary

AccelerComm Ltd in Cambridge is seeking a Design Team Leader to drive the hardware design of next-generation baseband and signal processing IP for 5G and space-qualified devices. You will lead a cross-disciplinary team of engineers, shaping the technical roadmap and delivering high‑quality RTL designs on FPGA and ASIC.

The role is hands-on with a strong focus on mentoring, timely project delivery, and collaboration with algorithm, system architecture and software teams.

Qualifications

• Track record of building and leading high performing collaborative teams.
• Expert knowledge of RTL design (Verilog, SystemVerilog) for complex ASIC and FPGA products.
• A strong skillset in delivery of digital designs for ASIC and FPGA.
• Optimisation of timing and hardware resources for high throughput data or signal processing applications.
• Experience with power management techniques, synthesis and timing analysis.
• Expert user of EDA tools for simulation and synthesis.
• Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall, requirements capture and traceability.

Responsibilities

• Inform technical decision‑making and planning within the wider company, working with colleagues from Algorithm, System Architecture and Software teams.
• Take responsibility for the successful and timely delivery of projects by providing technical leadership
• Provide team leadership to build knowledge and support the development of individuals
• Work closely with other senior members of the hardware team to help translate product requirements into hardware team deliverables.
• Support discussions with customers during presales and product development
• Oversee the implementation of designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches
• Help to shape AccelerComm’s engineering methodology, processes, and design techniques, integrating AI where valuable.
• Nurture professional growth of team members through regular mentoring, coaching, and feedback

Skills

RTL design

ASIC/FPGA

EDA tools

Project management

Agile/Waterfall

UVM verification

Tools

Verilog/SystemVerilog

UVM

Job description

AccelerComm Ltd in Cambridge is seeking a Design Team Leader to drive the hardware design of next-generation baseband and signal processing IP for 5G and space-qualified devices. You will lead a cross-disciplinary team of engineers, shaping the technical roadmap and delivering high‑quality RTL designs on FPGA and ASIC.

The role is hands-on with a strong focus on mentoring, timely project delivery, and collaboration with algorithm, system architecture and software teams.