Senior Design Engineer - Satellite 5G FPGA/ASIC (Hybrid)

AccelerComm Ltd; Cambridge; Hybride; GBP 70 000 - 95 000; Plein temps

Avantages offerts par ce poste

Bonus up to 20% of salary

EMI share options

Pension

Private health insurance

Hybrid working hours

Résumé du poste

AccelerComm Ltd. in Cambridge seeks multiple Senior Design Engineers to work on space-qualified 5G base station technology, delivering RTL for ASIC/FPGA, and collaborating across architecture, design, and verification teams.

You will implement FPGA/ASIC designs, develop testbenches, and deploy on latest platforms while following the company’s engineering processes. Hybrid working is offered, with roles based in Cambridge and other sites.

Qualifications

• Expert knowledge of RTL languages (Verilog, SystemVerilog) for complex ASIC/FPGA products.
• Strong skillset in delivering digital designs for ASIC/FPGA.
• Timing/resource optimization for high-throughput data or signal processing; power management, synthesis, timing analysis.
• Track record collaborating across teams to deliver integrated solutions.
• Experience with design documentation—specifications, user guides, verification plans.
• Expert user of EDA tools for simulation and synthesis.

Responsabilités

• Work with Algorithm and System Architecture teams to translate requirements into RTL mirco-architectures.
• Implement designs for FPGA/ASIC using industry-standard techniques and testbenches.
• Deploy designs onto FPGA development platforms for validation and integration.
• Adhere to AccelerComm engineering methodology and improve design flow efficiency and quality.
• Collaborate across the full design flow: micro-architecture, design, verification, physical implementation and optimization.

Connaissances

RTL/Verilog

SystemVerilog

ASIC/FPGA design

Timing optimization

EDA tools

Cross-team collaboration

Technical writing

UVM verification

C++/SystemC modeling

High-speed interfaces (PCIe/JESD)

Python scripting

Description du poste

AccelerComm Ltd. in Cambridge seeks multiple Senior Design Engineers to work on space-qualified 5G base station technology, delivering RTL for ASIC/FPGA, and collaborating across architecture, design, and verification teams.

You will implement FPGA/ASIC designs, develop testbenches, and deploy on latest platforms while following the company’s engineering processes. Hybrid working is offered, with roles based in Cambridge and other sites.