Senior RTL Design Engineer - Space/Telecom (Hybrid)

AccelerComm Ltd; West of England; Hybrid; GBP 75,000 - 100,000; Full time

Benefits offered by this job

Bonus up to 20% of salary

EMI share options

Pension

Private health insurance

Hybrid working hours

Job summary

AccelerComm Ltd in Bristol is seeking multiple Senior Design Engineers to develop space-qualified RTL IP for next-generation non-terrestrial 5G base stations aboard satellites. You will contribute to standalone and integrated IP using FPGA and ASIC approaches.

You will work with algorithms, system architecture and verification teams, applying AccelerComm design methodology to achieve high-throughput, low-power, reliable communications across challenging environments.

Qualifications

• Expert knowledge of RTL languages (Verilog, SystemVerilog) for complex ASIC/FPGA products.
• Experience delivering digital designs in ASIC/FPGA.
• Optimization of timing and hardware resources for high-throughput data or signal processing.
• Track record collaborating across teams to deliver integrated solutions.
• Experience with design documentation writing and verification planning.

Responsibilities

• Translate requirements into micro-architectures for RTL implementations.
• Implement designs for FPGA/ASIC using standard techniques and testbenches.
• Deploy designs on FPGA development platforms for validation and integration.
• Adhere to AccelerComm engineering processes and improve efficiency and quality.
• Collaborate across the full design flow: micro-architecture, design, verification, physical implementation and optimization.

Skills

Verilog

SystemVerilog

Digital design

Timing optimization

EDA tools

C++/SystemC

High-speed interfaces

Tools

EDA tools

C++/SystemC

Job description

AccelerComm Ltd in Bristol is seeking multiple Senior Design Engineers to develop space-qualified RTL IP for next-generation non-terrestrial 5G base stations aboard satellites. You will contribute to standalone and integrated IP using FPGA and ASIC approaches.

You will work with algorithms, system architecture and verification teams, applying AccelerComm design methodology to achieve high-throughput, low-power, reliable communications across challenging environments.