Hardware Design Engineer – Space-Grade FPGA/ASIC

Eauzone Spa; Southampton; Hybrid; GBP 55,000 - 75,000; Full time

Benefits offered by this job

Bonus up to 20%

EMI share options

Pension

Private health insurance

Job summary

AccelerComm is hiring a Hardware Design Engineer in Southampton to contribute to next-gen non-terrestrial communications and space-qualified devices. You will translate requirements into RTL architectures and implement FPGA/ASIC designs with testbenches, collaborating with architecture, verification and physical implementation teams to deliver high-performance IP.

The role involves working with Verilog/SystemVerilog/VHDL, EDA tools, and advanced interfaces; a strong emphasis on verification

Qualifications

• Proficient in RTL languages (Verilog, SystemVerilog, or VHDL) for complex ASIC/FPGA products.
• Experience delivering digital designs in ASIC/FPGA industries.
• Strong collaboration across teams to deliver integrated solutions.
• Experience writing design specifications, user guides and verification plans.
• Experienced with EDA tools for simulation and synthesis.

Responsibilities

• Translate requirements into micro-architectures for RTL implementations.
• Implement FPGA/ASIC designs with testbenches and verification support.
• Work with the design flow across architecture, verification, and physical implementation.
• Adhere to engineering methodologies and suggest improvements for efficiency and quality.
• Collaborate across micro-architecture, design, verification and physical implementation teams.

Skills

RTL languages

Digital design

Cross-team collaboration

Technical documentation

EDA tools

Tools

PCIe / PCI-E

JESD

AMBA bus protocols

UVM verification

SystemC/C++ modelling

Job description

AccelerComm is hiring a Hardware Design Engineer in Southampton to contribute to next-gen non-terrestrial communications and space-qualified devices. You will translate requirements into RTL architectures and implement FPGA/ASIC designs with testbenches, collaborating with architecture, verification and physical implementation teams to deliver high-performance IP.

The role involves working with Verilog/SystemVerilog/VHDL, EDA tools, and advanced interfaces; a strong emphasis on verification