Senior Design Engineer

AccelerComm Ltd; Cambridge; Ibrido; GBP 70.000 - 95.000; Tempo pieno

Vantaggi offerti da questo lavoro

Bonus up to 20% of salary

EMI share options

Pension

Private health insurance

Hybrid working hours

Descrizione del lavoro

AccelerComm Ltd. in Cambridge seeks multiple Senior Design Engineers to work on space-qualified 5G base station technology, delivering RTL for ASIC/FPGA, and collaborating across architecture, design, and verification teams.

You will implement FPGA/ASIC designs, develop testbenches, and deploy on latest platforms while following the company’s engineering processes. Hybrid working is offered, with roles based in Cambridge and other sites.

Competenze

• Expert knowledge of RTL languages (Verilog, SystemVerilog) for complex ASIC/FPGA products.
• Strong skillset in delivering digital designs for ASIC/FPGA.
• Timing/resource optimization for high-throughput data or signal processing; power management, synthesis, timing analysis.
• Track record collaborating across teams to deliver integrated solutions.
• Experience with design documentation—specifications, user guides, verification plans.
• Expert user of EDA tools for simulation and synthesis.

Mansioni

• Work with Algorithm and System Architecture teams to translate requirements into RTL mirco-architectures.
• Implement designs for FPGA/ASIC using industry-standard techniques and testbenches.
• Deploy designs onto FPGA development platforms for validation and integration.
• Adhere to AccelerComm engineering methodology and improve design flow efficiency and quality.
• Collaborate across the full design flow: micro-architecture, design, verification, physical implementation and optimization.

Conoscenze

RTL/Verilog

SystemVerilog

ASIC/FPGA design

Timing optimization

EDA tools

Cross-team collaboration

Technical writing

UVM verification

C++/SystemC modeling

High-speed interfaces (PCIe/JESD)

Python scripting

Descrizione del lavoro

Department: Hardware

Location: Cambridge

We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency.

We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency. You will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions. This is a Cambridge based role; please also take a look at our vacancies in Southampton and Bristol.

Key Responsibilities

• Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into mirco-architectures for RTL implementations
• Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches
• Deploy your designs onto the latest FPGA development platforms for validation and system integration
• Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
• Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA

Skills, Knowledge & Expertise

Essential

• Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
• A strong skillset in delivering digital designs in the ASIC and FPGA industry
• Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
• Track record in collaborating across teams to produce integrated solutions
• Experience in technical documentation writing - design specifications, user guides, verification plans
• Expert user of EDA tools for simulation and synthesis

Desirable

• Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
• Familiarity with the AMBA bus protocols
• Understanding of UVM verification techniques or practical experience using UVM for IP verification
• Experience using C++/SystemC for design modelling and integration
• Experience with high speed interfaces such as PCI-E or JESD
• Knowledge of a scripting language, such as Python
• Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
• Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools

Job Benefits

We pay competitive salaries which depend on skills and experience.

We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to EMI share options, issued periodically. We offer a range of good quality company benefits including pension and private health insurance.

We operate flexible working hours and offer hybrid working.