Space-Grade FPGA/ASIC Design Engineer (Hybrid)

AccelerComm Ltd; Bristol; Hybrid; GBP 60,000 - 95,000; Full time

Benefits offered by this job

Bonus up to 20% of salary

EMI share options

Pension

Private health insurance

Flexible working hours

Hybrid working

Job summary

AccelerComm Ltd in Bristol is seeking multiple Senior Design Engineers to work on space-qualified DSP hardware for non-terrestrial communications, including a 5G base station for satellites. You will contribute to RTL design across FPGA and ASIC, delivering IP blocks and testbenches.

The role offers hybrid working with global impact and close collaboration across engineering functions, enabling development of cutting-edge baseband solutions and EMI share options.

Qualifications

• Experience in RTL design for ASIC/FPGA environments.
• Strong timing and resource optimisation for high-throughput processing.
• Proven ability to collaborate across design teams and write technical docs.
• Expertise with EDA tools for simulation and synthesis.
• Familiarity with C++/SystemC for modelling is a plus.

Responsibilities

• Translate requirements into RTL micro-architectures for ASIC/FPGA implementations.
• Create testbenches and implement designs targeting FPGA and ASIC.
• Validate designs on FPGA platforms and integrate into systems.
• Improve design flow, processes and quality across the project lifecycle.
• Collaborate across micro-architecture, design, verification and physical implementation.

Job description

AccelerComm Ltd in Bristol is seeking multiple Senior Design Engineers to work on space-qualified DSP hardware for non-terrestrial communications, including a 5G base station for satellites. You will contribute to RTL design across FPGA and ASIC, delivering IP blocks and testbenches.

The role offers hybrid working with global impact and close collaboration across engineering functions, enabling development of cutting-edge baseband solutions and EMI share options.