Design Team Lead - RTL for FPGA/ASIC

AccelerComm Ltd; Cambridge; Hybrid; GBP 90,000 - 140,000; Full time

Benefits offered by this job

Bonus up to 20%

EMI share options

Pension

Private health insurance

Hybrid working

Job summary

AccelerComm Ltd seeks a Design Team Leader to guide a hardware team focused on 5G base stations and space-qualified devices. You will drive IP development, work across Algorithm, System Architecture and Software, and ensure on-time delivery of complex FPGA/ASIC designs with UVM testing.

The role emphasizes leadership, hands-on design, and shaping engineering methodologies, with hybrid options and a competitive benefits package.

Qualifications

• Leadership track record in building and leading high-performing teams.
• Expert knowledge of RTL design (Verilog, SystemVerilog) for ASIC/FPGA.
• Delivery of digital designs for ASIC/FPGA with timing/resource optimization.
• Power management techniques, synthesis and timing analysis.
• Experience with UVM verification approaches is desirable.
• Understanding of multi-disciplinary hardware design and integration.

Responsibilities

• Lead the hardware design team delivering Layer 1 IP for FPGA/ASIC.
• Inform technical decisions and planning across Algorithm, System Architecture and Software.
• Ensure timely delivery of projects with strong technical leadership.
• Mentor and develop team members through regular coaching and feedback.
• Translate product requirements into hardware deliverables with senior team.
• Engage with customers during presales and product development.
• Oversee designs using industry-standard techniques and UVM testbenches.
• Help shape engineering processes and incorporate AI where beneficial.

Skills

RTL design

ASIC/FPGA design

Timing optimization

EDA tools

Project management

Power management

UVM verification (Desirable)

Job description

AccelerComm Ltd seeks a Design Team Leader to guide a hardware team focused on 5G base stations and space-qualified devices. You will drive IP development, work across Algorithm, System Architecture and Software, and ensure on-time delivery of complex FPGA/ASIC designs with UVM testing.

The role emphasizes leadership, hands-on design, and shaping engineering methodologies, with hybrid options and a competitive benefits package.