Senior Design Engineer – Hybrid (FPGA/ASIC)

AccelerComm Ltd; West of England; Hybrid; GBP 70,000 - 105,000; Full time

Benefits offered by this job

Bonus up to 20% of salary

EMI share options

Pension

Private health insurance

Flexible working hours

Hybrid working

Job summary

AccelerComm Ltd in Bristol is seeking Senior Design Engineers to work on space-qualified 5G base station technology for satellite deployment. You will deliver RTL designs for ASIC/FPGA, collaborate across architecture, verification, and implementation teams, and deploy on FPGA platforms.

The role involves working with the hardware department on cutting-edge non-terrestrial communications and offers hybrid working arrangements within Bristol, plus opportunities to contribute to EMI.

Qualifications

• Expert knowledge of RTL languages (Verilog/SystemVerilog) for complex ASIC/FPGA products.
• A strong skillset in delivering digital designs in the ASIC and FPGA industry.
• Optimization of timing and hardware resources for high-throughput data or signal processing.
• Track record in collaborating across teams to produce integrated solutions.
• Experience in technical documentation writing – design specifications and verification plans.
• Expert user of EDA tools for simulation and synthesis.
• Knowledge of communications signal processing algorithms (e.g., error correction).
• Familiarity with the AMBA bus protocols.
• Experience with C++/SystemC for design modelling and integration.
• Experience with high-speed interfaces such as PCIe or JESD.
• Python scripting knowledge.

Responsibilities

• Work closely with Algorithm and System Architecture teams to translate requirements into RTL micro-architectures.
• Implement designs targeting FPGA and ASIC using standard techniques with testbenches.
• Deploy designs onto FPGA development platforms for validation and integration.
• Engage with engineering methodology and propose efficiency/quality improvements.
• Collaborate across design flow: micro-architecture, design, verification, and physical implementation.

Skills

Verilog/SystemVerilog

ASIC/FPGA design

Timing/Resource optimization

Cross-functional collaboration

Documentation writing

EDA tool proficiency

Tools

EDA tools (simulation & synthesis)

PCIe/JESD high-speed interfaces

Job description

AccelerComm Ltd in Bristol is seeking Senior Design Engineers to work on space-qualified 5G base station technology for satellite deployment. You will deliver RTL designs for ASIC/FPGA, collaborate across architecture, verification, and implementation teams, and deploy on FPGA platforms.

The role involves working with the hardware department on cutting-edge non-terrestrial communications and offers hybrid working arrangements within Bristol, plus opportunities to contribute to EMI.