Senior Design Engineer - 5G Satellite FPGA/ASIC

AccelerComm Ltd; Southampton; On-site; GBP 65,000 - 90,000; Full time

Job summary

AccelerComm Ltd in Southampton, UK, is seeking multiple Senior Design Engineers to enable space-qualified 5G base stations deployed on satellites. You will develop RTL for ASIC/FPGA, targeting both FPGA and ASIC platforms, delivering standalone IP and integrated IP solutions.

You will collaborate with algorithm and system architecture teams, implement testbenches, use the latest EDA tools, and contribute to optimization across design, verification, and physical implementation.

Qualifications

• Expert knowledge of an RTL language for complex ASIC/FPGA products.
• Strong skillset delivering digital designs in ASIC/FPGA.
• Optimization of timing and hardware resources for high throughput data/signal processing; includes power management, synthesis, timing analysis.
• Track record collaborating across teams to deliver integrated solutions.
• Experience writing design specs, user guides, verification plans.

Responsibilities

• Translate requirements into micro-architectures for RTL implementations.
• Create testbenches and deploy designs on FPGA/ASIC platforms.
• Validate designs on FPGA development platforms; support system integration.
• Follow AccelerComm engineering methodology and contribute improvements to design flow and product quality.
• Collaborate with micro-architecture, design, verification, and physical implementation teams.

Skills

RTL Verilog/SystemVerilog

ASIC/FPGA design

Timing/resource optimization

Cross-team collaboration

Technical documentation

EDA tools

Tools

Verilog/SystemVerilog tools

FPGA/ASIC development platforms

Job description

AccelerComm Ltd in Southampton, UK, is seeking multiple Senior Design Engineers to enable space-qualified 5G base stations deployed on satellites. You will develop RTL for ASIC/FPGA, targeting both FPGA and ASIC platforms, delivering standalone IP and integrated IP solutions.

You will collaborate with algorithm and system architecture teams, implement testbenches, use the latest EDA tools, and contribute to optimization across design, verification, and physical implementation.