Senior ASIC Design Engineer — Space-Grade Silicon & Systems

SpaceX; Irvine; On-site; GBP 121,000 - 168,000; Full time

Job summary

A leading aerospace manufacturer in Irvine is seeking a Sr. ASIC Design Engineer to develop next-generation FPGAs and ASICs for space and ground systems. Your role involves evaluating architectural trade-offs, defining micro-architecture, and collaborating with verification teams. Ideal candidates will have at least 5 years of experience in RTL implementation and a relevant degree. Competitive compensation between $160,000 – $220,000 per year, with comprehensive benefits included.

Benefits

Comprehensive medical, vision, and dental coverage

401(k) retirement plan

Paid vacation and holidays

Qualifications

• 5+ years of experience in RTL implementation.
• Experience with standard bus protocols (e.g. AXI, AHB).
• Scripting skills (Python, TCL etc.) are beneficial.

Responsibilities

• Evaluate architectural trade-offs based on features and requirements.
• Define micro-architecture, implement RTL in Verilog/System Verilog.
• Work closely with the verification team for coverage.

Skills

Problem-solving

Teamwork

Dynamic environment adaptability

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

EDA tools such as HDL simulators

Xilinx Vivado

Altera Quartus II

Job description

A leading aerospace manufacturer in Irvine is seeking a Sr. ASIC Design Engineer to develop next-generation FPGAs and ASICs for space and ground systems. Your role involves evaluating architectural trade-offs, defining micro-architecture, and collaborating with verification teams. Ideal candidates will have at least 5 years of experience in RTL implementation and a relevant degree. Competitive compensation between $160,000 – $220,000 per year, with comprehensive benefits included.